Processor Status (Ps); Fig. 2.19 Configuration Of Processor Status (Ps) - Fujitsu MB90420/5 (A) Series Hardware Manual

2.7.3 Processor Status (PS)

The processor status (PS) consists of the bits controlling CPU and various bits indicating the CPU status.
The PS register consists of the following three registers.
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
n Configuration of processor status (PS)
The processor status (PS) consists of bits controlling CPU and various bits indicating the CPU status.
Figure 2.19 shows the configuration of the processor status (PS).
ILM
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
PS ILM2 ILM1 ILM0 B4
Initial value
0 0
— : Not used
X : Undefined
• Interrupt level mask register (ILM)
This register indicates the level of the interrupt that the CPU is currently accepting. The value of this
register is compared to the value of the interrupt level setting bits of the interrupt control register (ICR: IL0
to IL2) corresponding to the interrupt request of each peripheral resource.
• Register bank pointer (RP)
This pointer specifies the starting address of the memory block (register bank) used as the general-
purpose register in the RAM area.
General-purpose registers have 32 banks in total and these banks are specified by setting 0 to 31 in the
RP.
• Condition code register (CCR)
This register consists of various flags that are set (1) or reset (0) by instruction execution result or
generatio of an interrupt.
RP
bit 9
B3 B2 B1
0 0 0 0

Fig. 2.19 Configuration of Processor Status (PS)

CPU
bit 8 bit 7 bit 6 bit 5
B0 — I
0 0 — 0
2-21
CCR
bit 4 bit 3 bit 2 bit 1
S T N Z
1 X X X
bit 0
V C
X X