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3.7.3
Processor Status (PS)
The processor status (PS) consists of CPU control bits and bits that indicate the CPU
status. The PS register consists of the following three registers:
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Processor Status (PS) Configuration
The processor status (PS) consists of CPU control bits and bits that indicate the CPU status. Figure 3.7-8
shows the configuration of the processor status (PS)
Default value ⇒
Default value ⇒
Default value ⇒
Default value ⇒
●
Interrupt level mask register (ILM)
This register indicates the level of the interrupt currently accepted by the CPU. The value is compared with
the value of the interrupt level setting bits (ICR: IL0 to IL2) in the interrupt control register set for the
peripheral resource interrupt request.
●
Register bank pointer (RP)
This pointer points to the first address of the memory block (register bank) used as the general-purpose
register in the RAM area.
There are 32 banks for general-purpose registers. Values 0 to 31 are set in the RP to specify a bank.
●
Condition code register (CCR)
This register consists of flags that are set to "1" or reset to "0" by instruction execution results and by
interrupts.
Figure 3.7-8 Processor Status (PS) Configuration
bit
15
13 12
PS
ILM
RP
000
00000
7
6
5
4
bit
–
I
S
T
N
–
0
1
x
x
bit
12
11
10
9
B4 B3 B2 B1 B0
0
0
0
0
bit
15
14
ILM2
ILM1
ILM0
0
0
8 7
CCR
-01xxxxx
3
2
1
0
Z
V
C
: CCR
x
x
x
8
: RP
0
13
: ILM
0
CHAPTER 3 CPU
0
- : Not used
x : Undefined
47
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