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Each cache function is downloaded through JTAG in 33 bit packets.
formats for each of the JTAG cache functions. Invalidate IC Line and Invalidate Mini IC each
require 1 packet. Load Main IC and Load Mini IC each require 9 packets.
Figure 10-10. Format of LDIC Cache Functions
All packets are 33 bits in length. Bits [2:0] of the first packet specify the function to execute. For
functions that require an address, bits[32:6] of the first packet specify an 8-word aligned address
(Packet1[32:6] = VA[31:5]). For Load Main IC and Load Mini IC, 8 additional data packets are
used to specify 8 ARM* instructions to be loaded into the target instruction cache. Bits[31:0] of the
data packets contain the data to download. Bit[32] of each data packet is the value of the parity for
the data in that packet.
As shown in
packet, the host must take the JTAG state machine into the Update_DR state. After the host does an
Update_DR and returns the JTAG state machine back to the Shift_DR state, the host can
immediately begin shifting in the next 33-bit packet.
10.13.4
Loading IC During Reset
Code can be downloaded into the instruction cache through JTAG during a processor reset. This
feature is used during software debug to download the debug handler prior to starting an
application program. The downloaded handler can then intercept the reset vector and do any
necessary setup before the application code executes.
Any code downloaded into the instruction cache through JTAG, must be downloaded to addresses
that are not already valid in the instruction cache. Failure to meet this requirement will result in
unpredictable behavior by the processor. During a processor reset, the instruction cache is typically
invalidated, with the exception of the following modes:
•
LDIC mode: active when LDIC JTAG instruction is loaded in the JTAG IR; prevents the mini
instruction cache and the main instruction cache from being invalidated during reset.
Intel® XScale™ Microarchitecture User's Manual
Invalidate IC Line
Invalidate Mini IC
Load Main IC
(CMD = 0b010)
and
Load Mini IC
(CMD = 0b011)
Figure
10-10, the first bit shifted in TDI is bit 0 of the first packet. After each 33-bit
VA[31:5]
0
0 0
0 0
32
31
5
2
x x
x 0
. . .
0 0
0 0
32
31
5
2
P
Data Word 7
.
.
.
Data Word 0
P
VA[31:5]
0 0 0
CMD
32
31
5
2
Software Debug
Figure 10-10
shows the packet
0
0
1
- indicates first
bit shifted in
0
- indicates last
bit shifted in
0
10-33
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