Topology 2C: Cmos Signals Driven By Ich4-M - A20M#, Ignne#, Lint0/Intr, Lint1/Nmi, Slp#, Smi#, And Stpclk; Topology 3: Cmos Signals Driven By Ich4-M To Cpu And Fwh - Init; Figure 15. Routing Illustration For Topology 2C; Table 10. Layout Recommendations For Topology 2C - Intel 852GM Design Manual

Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines
4.3.4.6. Topology 2C: CMOS Signals Driven by ICH4-M – A20M#, IGNNE#,
LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK#
The Topology 2C CMOS A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK#
signals should implement a point-to-point connection between the ICH4-M and the Mobile Intel
Pentium 4 Processor–M. The routing guidelines allow both signals to be routed as either micro-strip or
strip-lines using 55 Ω ± 15% characteristic trace impedance. No additional motherboard components are
necessary for this topology.

Figure 15. Routing Illustration for Topology 2C

Table 10. Layout Recommendations for Topology 2C

4.3.4.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH – INIT#
The signal INIT# should adhere to the following routing and layout recommendations.
Table 11 lists the recommended routing requirements for the INIT# signal of the ICH4-M. The routing
guidelines allow both signals to be routed as either micro-strip or strip-lines using 55 Ω ± 15%
characteristic trace impedance.
Figure 16 shows the recommended implementation for providing voltage translation between the ICH4-
M's INIT# voltage signaling level and any firmware hub (FWH) that utilizes a 3.3-V interface voltage
(shown as a supply 3.3V). For convenience, the entire topology and required transistors and resistors for
the voltage translator is shown in Figure 16.
Series resistor Rs is a component of the voltage translator logic circuit and serves as a driver isolation
resistor. Rs is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1, to
emphasize the placement of Rs with respect to Q1. The routing recommendations of transmission line
L3 in Figure 16 is listed in
Table 11 and Rs should be placed at the beginning of the T-split of the trace from the ICH4-M's INIT#
pin.
44
CPU
L1
0.5" – 12.0"
0.5" – 12.0"
ICH4-M
L1
Transmission Line Type
Micro-strip
Strip-line
®
Intel 852GM Chipset Platform Design Guide
R