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11.7 EXTERNAL INTERRUPTS (INT
There are two external interrupt sources: INT
An interrupt request is issued when a rising or falling edge is input to the INT
11.7.1 Configuration
Fig. 11-5 shows the configurations of the INT
As shown in Fig. 11-5, the INT
detectors.
The edge detectors output their respective interrupt request signals according to the inputs from the pin
and the status of the IEGNC or IEGVSYN flip-flop.
The IEGNC flip-flop and IEGVSYN flip-flop correspond to the IEGNC flag and IEGVSYN flag, respectively,
in the interrupt edge selection register (INTEDGE: address 1FH) of the control register.
The INTNC latch and INTVSYN latch correspond to the INTNC flag and INTVSYN flag, respectively, in the
interrupt-pin-level judge register (INTJDG: address 0FH) of the control register.
The Schmitt triggers at the INT
not accept pulses of 1 s or less.
A minimum pulse width can be set for the INT
INT
pin
NC
Schmitt trigger
V
pin
SYNC
Schmitt trigger
PIN, V
PIN)
NC
SYNC
NC
and V
NC
and V
signals are input to the INTNC or INTVSYN latch and to edge
NC
SYNC
and V
inputs prevent pulses operations due to noise. These pins do
NC
SYNC
NC
Fig. 11-5 INT
Pin and INT
0
Control register
Interrupt
Interrupt
edge select
pin level judge
Name
(INTEDGE)
(INTJDG)
Address
1 FH
Bit
b
b
b
b
b
b
3
2
1
0
3
I
I
E
E
0
G
0
0
Flag
G
V
symbol
N
S
Y
C
N
INTNC latch
IEGNC flip-flop
INTVSYN latch
IEGVSYN flip-flop
and V
.
SYNC
interrupts.
SYNC
pin. See Section 9.10.
Pin Configurations
1
0 FH
b
b
2
1
0
I
I
N
N
T
0
T
V
N
S
Y
C
N
Edge detection
Edge detection
PD17062
or V
pin.
NC
SYNC
Interrupt request block
IRQNC
IRQVSYN
121
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