Terminal Count Output Upon Dma Transfer End; Forcible Interruption - NEC V850E/MA1 User Manual

6.11 Terminal Count Output upon DMA Transfer End

The terminal count signal (TCn) becomes active for one clock during the last DMA transfer cycle (n = 3 to 0).
The TCn signal becomes active in the clock following the clock in which the BCYST signal becomes active during
the last DMA transfer cycle. In 2-cycle transfer, the TCn signal becomes active in the write cycle of the last DMA
transfer.
DMARQn (input)
TCn (output)
Remark n = 0 to 3

6.12 Forcible Interruption

DMA transfer can be forcibly interrupted by NMI input during DMA transfer.
At such a time, the DMAC resets the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer
disabled state is entered. An NMI request can then be acknowledged after the DMA transfer that was being executed
when the NMI was input is complete (n = 0 to 3).
In the single-step transfer mode or block transfer mode, the DMA transfer request is held in the DMAC. If the Enn
bit is set to 1, DMA transfer restarts from the point where it was interrupted.
In the single transfer mode, if the Enn bit is set to 1, the next DMA transfer request is received and DMA transfer
starts.
NMI (input)
DDIS register
DRST register
E00 bit of DCHC register
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-21. Terminal Count Signal (TCn) Timing Example
CPU CPU CPU DMAn DMAn DMAn CPU
Figure 6-22. Example of Forcible Interrupt of DMA Transfer
Forcible
interruption
DMA transfer DMA transfer stop
User's Manual U14359EJ4V0UM
DMA channel n terminal count
Transfer Forcible
restart interruption
DMA transfer DMA transfer stop
01H
01H
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