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13.8 DMA Channel Priorities
The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
These priorities are valid in the TI state only. In the block transfer mode, the channel used for transfer is never
switched.
In the single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is released (in the
TI state), the higher priority DMA transfer request is acknowledged.
13.9 DMA Transfer Start Factors
There are two types of DMA transfer start factors, as shown below.
(1) Request from software
If the STGn, Enn, and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3).
• STGn bit = 1
• Enn bit = 1
• TCn bit = 0
(2) Request from on-chip peripheral I/O
If, when the Enn and TCn bits of the DCHCn register are set as shown below, an interrupt request is issued
from the on-chip peripheral I/O that is set in the DTFRn register, DMA transfer starts (n = 0 to 3).
• Enn bit = 1
• TCn bit = 0
13.10 DMA Transfer End
13.10.1 DMA transfer end interrupt
When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt
(INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3).
13.10.2 Terminal count output upon DMA transfer end
The terminal count signal becomes active for one clock during the last DMA transfer cycle.
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CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER)
Preliminary User's Manual U15905EJ1V0UD
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