Page 1 User’s Manual µ µ µ µ PD789026 Subseries 8-Bit Single-Chip Microcontrollers µ µ µ µ PD789022 µ µ µ µ PD789024 µ µ µ µ PD789025 µ µ µ µ PD789026 µ µ µ µ PD78F9026A Document No. U11919EJ3V0UMJ1 (3rd edition) Date Published October 2000 N CP(K) ©...
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Page 3: Table Of Contents
SUMMARY OF CONTENTS CHAPTER 1 GENERAL ............................23 CHAPTER 2 PIN FUNCTIONS..........................33 CHAPTER 3 CPU ARCHITECTURE.........................41 CHAPTER 4 PORT FUNCTIONS........................69 CHAPTER 5 CLOCK GENERATION CIRCUIT ....................85 CHAPTER 6 16-BIT TIMER ..........................93 CHAPTER 7 8-BIT TIMER/EVENT COUNTER....................105 CHAPTER 8 WATCHDOG TIMER ........................115 CHAPTER 9 SERIAL INTERFACE 00......................121 CHAPTER 10 INTERRUPT FUNCTIONS ......................149...
Page 4 Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 5 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 6 Major Revision in This Edition Page Description Completion of development of µ PD789022 and µ PD789024 Throughout Change of part number from µ PD78F9026 to µ PD78F9026A Deletion of following products: µ PD789022CU-×××, 789024CU-××× Addition of GB-8ES type package to all models p.39 Change of circuit type and recommended connection of unused pins in Table 2-1 p.99...
Page 7 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
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Page 9 INTRODUCTION Readers This manual is intended for user engineers who understand the functions of the µ PD789026 Subseries to design and develop its application systems and programs. The target subseries is the µ PD789026 Subseries, which consists of the µ PD789022, µ PD789024, µ PD789025, µ PD789026, and µ PD78F9026A. Purpose This manual is designed to deepen your understanding of the following functions described in the following organization.
Page 10 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents Document Name Document No. English Japanese µ PD789022, 789024, 789025, 789026 Data Sheet U11715E U11715J µ PD78F9026A Data Sheet U14356E U14356J µ...
Page 11 Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Device C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
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Page 13 TABLE OF CONTENTS CHAPTER 1 GENERAL..........................23 Features ............................23 Applications..........................23 Ordering Information .........................24 Pin Configuration (Top View)....................25 Development of 78K/0S Series....................28 Block Diagram ..........................30 Outline of Functions ........................31 CHAPTER 2 PIN FUNCTIONS ........................33 List of Pin Functions........................33 Description of Pin Functions ....................35 2.2.1 P00 to P07 (Port 0)........................35 2.2.2...
Page 14 3.3.2 Immediate addressing .........................61 3.3.3 Table indirect addressing ......................62 3.3.4 Register addressing ........................62 Operand Address Addressing ....................63 3.4.1 Direct addressing ........................63 3.4.2 Short direct addressing .......................64 3.4.3 Special function register (SFR) addressing.................65 3.4.4 Register addressing ........................66 3.4.5 Register indirect addressing......................67 3.4.6 Based addressing........................68 3.4.7...
Page 15 6.4.2 Operation as timer output ......................101 6.4.3 Capture operation........................102 6.4.4 16-bit timer counter 20 readout ....................103 CHAPTER 7 8-BIT TIMER/EVENT COUNTER ..................105 8-Bit Timer/Event Counter Functions..................105 8-Bit Timer/Event Counter Configuration ................106 8-Bit Timer/Event Counter Control Registers................107 8-Bit Timer/Event Counter Operation..................109 7.4.1 Operation as interval timer ......................109 7.4.2...
Page 16 11.1.2 Standby function control register....................168 11.2 Operation of Standby Function ....................169 11.2.1 HALT mode ..........................169 11.2.2 STOP mode..........................172 CHAPTER 12 RESET FUNCTION......................175 CHAPTER 13 µ µ µ µ PD78F9026A ........................179 13.1 Flash Memory Programming....................180 13.1.1 Selecting communication mode....................180 13.1.2 Flash memory programming function ..................181 13.1.3...
Page 17 LIST OF FIGURES (1/3) Figure No. Title Page List of Pin Input/Output Circuits......................... 40 Memory Map ( µ PD789022) ........................41 Memory Map ( µ PD789024) ........................42 Memory Map ( µ PD789025) ........................43 Memory Map ( µ PD789026) ........................44 Memory Map ( µ...
Page 18 LIST OF FIGURES (2/3) Figure No. Title Page Block Diagram of 16-Bit Timer 20 ......................94 16-Bit Timer Mode Control Register 20 Format ..................97 Port Mode Register 5 Format........................98 Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation ........99 Timer Interrupt Operation Timing ......................100 Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation ........101 Timer Output Timing ..........................101...
Page 19 LIST OF FIGURES (3/3) Figure No. Title Page 10-4 External Interrupt Mode Register 0 Format ..................... 155 10-5 Program Status Word Configuration ....................... 156 10-6 Key Return Mode Register 00 Format..................... 157 10-7 Falling Edge Detection Circuit......................... 157 10-8 Flowchart from Non-Maskable Interrupt Request Generation to Acceptance ......... 159 10-9 Non-Maskable Interrupt Request Acceptance Timing................
Page 20 LIST OF TABLES (1/2) Table No. Title Page Type of Input/Output Circuit of Each Pin and Handling of Unused Pins ............39 Internal ROM Capacity..........................46 Vector Table...............................46 Internal High-Speed RAM Capacity ......................47 Special Function Registers ........................58 Port Functions ............................70 Port Configuration ............................71 Port Mode Register and Output Latch Settings when Using Alternate Functions........81 Configuration of Clock Generation Circuit....................85 Maximum Time Required for Switching CPU Clock ...................91...
Page 21 LIST OF TABLES (2/2) Table No. Title Page 10-2 Flags Corresponding to Interrupt Request Signal Name ................ 152 10-3 Time from Generation of Maskable Interrupt Request to Processing ............. 161 11-1 HALT Mode Operating Status ......................... 169 11-2 Operation after Release of HALT Mode ....................171 11-3 STOP Mode Operating Status.........................
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Page 23: Chapter 1 General
CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacity Item Program Memory Data Memory Part Number µ PD789022 4 Kbytes 256 bytes µ PD789024 8 Kbytes µ PD789025 12 Kbytes 512 bytes µ PD789026 16 Kbytes µ PD78F9026A Flash memory 16 Kbytes •...
Page 24: Ordering Information
CHAPTER 1 GENERAL 1.3 Ordering Information Part Number Package Internal ROM µ PD789022GB-×××-3BS-MTX 44-pin plastic QFP (10 × 10 mm, resin thickness 2.7 mm) Mask ROM µ PD789022GB-×××-8ES 44-pin plastic LQFP (10 × 10 mm, resin thickness 1.4 mm) Mask ROM µ...
Page 25: Pin Configuration (Top View)
CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) • 42-pin plastic shrink DIP (600 mil) µ PD789025CU-××× µ PD789026CU-××× µ PD78F9026ACU RESET IC (V P51/TO2 P40/KR0 P50/TI0/TO0 P41/KR1 P32/INTP2/CPT2 P42/KR2 P31/INTP1 P43/KR3 P30/INTP0 P44/KR4 P22/RxD/SI0 P45/KR5 P21/TxD/SO0 P46/KR6 P20/ASCK/SCK0 P47/KR7 Caution Connect the IC pin directly to V or V An item in parentheses applies to the µ...
Page 26 CHAPTER 1 GENERAL 44-pin plastic QFP (10 × × × × 10 mm, resin thickness 2.7 mm) • µ PD789022GB-×××-3BS-MTX µ PD789024GB-×××-3BS-MTX µ PD789025GB-×××-3BS-MTX µ PD789026GB-×××-3BS-MTX µ PD78F9026AGB-3BS-MTX 44-pin plastic LQFP (10 × × × × 10 mm, resin thickness 1.4 mm) •...
Page 27 CHAPTER 1 GENERAL ASCK : Asynchronous Serial Clock RESET : Reset CPT2 : Capture Trigger Input : Receive Data : Internally Connected SCK0 : Serial Clock INTP0 to INTP2 : Interrupt from Peripherals : Serial Input KR0 to KR7 : Key Return : Serial Output : Non-connection : Timer Input...
Page 28: Development Of 78K/0S Series
CHAPTER 1 GENERAL 1.5 Development of 78K/0S Series The following shows the history of 78K/0S Series product development. Subseries names are shown inside frames. In production Under development For small-scale, general- purpose applicationns µ µ Device developed by adding the subsystem clock to the PD789026 44-pin PD789046 µ...
Page 29 CHAPTER 1 GENERAL The following lists the main functional differences between subseries products. Function Timer 8-Bit 10-Bit Serial Interface Remark Capacity MIN. 8-Bit 16-Bit Watch WDT Value Subseries Name µ PD789046 − − − General 16 K 1 ch 1 ch 1 ch 1 ch 1 ch (UART: 1 ch)
Page 30: Block Diagram
CHAPTER 1 GENERAL 1.6 Block Diagram 8-bit TIMER TI0/TO0/P50 PORT0 P00 to P07 EVENT/COUNTER 00 PORT1 P10 to P17 TO2/P51 16-bit TIMER 20 CPT2/INTP2/P32 78K/0S CPU CORE PORT2 P20 to P22 WATCHDOG TIMER PORT3 P30 to P32 PORT4 P40 to P47 SCK0/ASCK/P20 SERIAL SO0/TxD/P21...
Page 31: Outline Of Functions
CHAPTER 1 GENERAL 1.7 Outline of Functions µ PD789022 µ PD789024 µ PD789025 µ PD789026 µ PD78F9026A Part Number Item Internal memory Mask ROM Flash Memory 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 16 Kbytes High-speed RAM 256 bytes 512 bytes 0.4/1.6 µ...
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Page 33: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions Port pins Pin Name Input/Output Function After Reset Alternate Function − P00 to P07 Input/output Port 0 Input 8-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO).
Page 34 CHAPTER 2 PIN FUNCTIONS Non-port pins Pin Name Input/Output Function After Reset Alternate Function INTP0 Input External interrupt request input for which the active edge (rising Input edge, falling edge, or both) can be specified INTP1 INTP2 P32/CPT2 KR0 to KR7 Input Key return signal detection Input...
Page 35: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set in the input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used in the pull-up resistor option register (PUO).
Page 36: P30 To P32 (Port 3)
CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P32 (Port 3) These pins constitute a 3-bit I/O port. In addition, they also function as external interrupt input and capture edge input. This port can drive LEDs directly. Port 3 can be specified in the following operation modes in bit-wise. Port mode In this mode, port 3 functions as a 3-bit I/O port.
Page 37: P50 To P53 (Port 5)
CHAPTER 2 PIN FUNCTIONS 2.2.6 P50 to P53 (Port 5) These pins constitute a 4-bit I/O port. In addition, these pins provide the function for performing input/output to/from the timer. This port can drive LEDs directly. Port 5 can be specified in the following operation modes in bit-wise. Port mode In this mode, port 5 functions as a 4-bit I/O port.
Page 38: Ic (Mask Rom Model Only)
CHAPTER 2 PIN FUNCTIONS 2.2.13 IC (mask ROM model only) The IC (Internally Connected) pin is used to set the µ PD789026 Subseries in the test mode in testing before shipment. In the normal operating mode, directly connect the IC pin to the V or V pin with as short a wire as possible.
Page 39: Pin Input/Output Circuits And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin Input/Output Circuits and Connection of Unused Pins Types of input/output circuits for pins and recommended connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, see Figure 2-1. Table 2-1.
Page 40 CHAPTER 2 PIN FUNCTIONS Figure 2-1. List of Pin Input/Output Circuits Type 8-J Type 2 Pullup P-ch enable Output data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Type 5-X Pullup P-ch enable Output data P-ch IN/OUT Output N-ch disable Port...
Page 41: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD789026 Subseries can access 64 Kbytes of memory space. Figures 3-1 through 3-5 show the memory maps. Figure 3-1. Memory Map ( µ µ µ µ PD789022) FFFFH Special Function Registers 256 ×...
Page 42 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ µ µ µ PD789024) FFFFH Special Function Registers 256 × 8 bits FF00H FEFFH Internal High-Speed RAM 256 × 8 bits FE00H FDFFH Reserved Data Memory Space 1FFFH 2000H 1FFFH Program Area 0080H Program...
Page 43 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( µ µ µ µ PD789025) FFFFH Special Function Registers 256 × 8 bits FF00H FEFFH Internal High-Speed RAM 512 × 8 bits FD00H FCFFH Reserved Data Memory Space 2FFFH 3000H 2FFFH Program Area 0080H Program...
Page 44 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map ( µ µ µ µ PD789026) FFFFH Special Function Registers 256 × 8 bits FF00H FEFFH Internal High-Speed RAM 512 × 8 bits FD00H FCFFH Reserved Data Memory Space 3FFFH 4000H 3FFFH Program Area 0080H Program...
Page 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( µ µ µ µ PD78F9026A) FFFFH Special Function Registers 256 × 8 bits FF00H FEFFH Internal High-Speed RAM 512 × 8 bits FD00H FCFFH Reserved Data Memory Space 3FFFH 4000H 3FFFH Program Area 0080H Program...
Page 46: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The µ PD789026 Subseries provides the internal ROMs (or flash memory) containing the following capacities on each product.
Page 47: Internal Data Memory (Internal High-Speed Ram) Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory (internal high-speed RAM) space The µ PD789026 Subseries provides internal high-speed RAM containing the following capacity on each product. The internal high-speed RAM can also be used as a stack memory. Table 3-3. Internal High-Speed RAM Capacity Part Number Capacity µ...
Page 48: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing The µ PD789026 Subseries provides a variety of addressing modes which take account of memory Note 1 manipulability, etc. Especially at address corresponding to data memory area (FE00H to FFFFH , FD00H to Note 2 FFFFH ), particular addressing modes are possible to meet the functions of the special function registers (SFR)
Page 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data Memory Addressing ( µ µ µ µ PD789024) FFFFH Special Function Registers (SFR) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short Direct Internal High-Speed RAM Addressing 256 × 8 bits FE20H FE1FH FE00H...
Page 50 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( µ µ µ µ PD789025) FFFFH Special Function Registers (SFR) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short Direct Internal High-Speed RAM Addressing 512 × 8 bits FE20H FE1FH FD00H...
Page 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing ( µ µ µ µ PD789026) FFFFH Special Function Registers (SFR) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short Direct Internal High-Speed RAM Addressing 512 × 8 bits FE20H FE1FH FD00H...
Page 52 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( µ µ µ µ PD78F9026A) FFFFH Special Function Registers (SFR) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short Direct Internal High-Speed RAM Addressing 512 × 8 bits FE20H FE1FH FD00H...
Page 53: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD789026 Subseries provides the following on-chip processor registers: 3.2.1 Control registers The control registers contains special functions to control the program sequence statuses and stack memory. A program counter, a program status word, and a stack pointer are control registers. Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 54 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the interrupt enabled (EI) status is set and interrupt request acknowledgement is controlled with an interrupt mask flag for each interrupt source.
Page 55 CHAPTER 3 CPU ARCHITECTURE Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-13. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10 SP9...
Page 56: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 57: Special Function Register (Sfr)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function register (SFR) Unlike a general-purpose register, each special function register has a special function. It is allocated in the 256-byte area FF00H to FFFFH. The special function register can be manipulated, like the general-purpose register, with the operation, transfer, and bit manipulation instructions.
Page 58 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits Ο Ο − FF00H Port 0 Ο Ο − FF01H Port 1 Ο...
Page 59 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits Ο Ο − FFE0H Interrupt request flag register 0 Ο Ο −...
Page 60: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 61: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces. [Illustration] In case of CALL !addr16 or BR !addr16 instruction CALL or BR...
Page 62: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the low-order-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 63: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 64: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal high- speed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 65: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 66: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] The general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with register specification code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 67: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specification code in the instruction code. This addressing can be carried out for all the memory spaces.
Page 68: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
Page 69: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Functions of Ports The µ PD789026 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Alternate functions are provided in addition to the digital I/O port function. For more information on these alternate functions, see Chapter 2.
Page 70 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name Input/Output Function After Reset Alternate Function − P00 to P07 Input/output Port 0 Input 8-bit I/O port I/O specifiable in 1-bit units When used as input port, on-chip pull-up resistor can be connected by setting of the pull-up resistor option register (PUO).
Page 71: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports have the following hardware configuration. Table 4-2. Port Configuration Parameter Configuration Control register Port mode register (PMm: m = 0 to 5) Pull-up resistor option register (PUO) Port Total: 34 (input/output: 34) Pull-up resistor Total: 34 (on-chip pull-up resistor can be connected by software) 4.2.1 Port 0...
Page 72: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is an 8-bit I/O port with output latch. Port 1 can be specified in the input or output mode in 1-bit units by using the port mode register 1 (PM1). When using P10 to P17 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register (PUO).
Page 73: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is a 3-bit I/O port with output latch. Port 2 can be specified in the input or output mode in 1-bit units by using the port mode register 2 (PM2). When using P20 to P22 pins as input port pins, on-chip pull-up resistors can be connected in 3-bit units by using the pull-up resistor option register (PUO).
Page 74 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 PUO2 P-ch PORT Output Latch (P21) P21/TxD/SO0 PM21 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal User's Manual U11919EJ3V0UM00...
Page 75 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 PUO2 P-ch Alternate Function PORT Output Latch P22/RxD/SI0 (P22) PM22 PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal User's Manual U11919EJ3V0UM00...
Page 76: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 3-bit I/O port with output latch. It can be specified in input or output mode in 1-bit units by using the port mode register 3 (PM3). When using P30 to P32 pins as input port pins, on-chip pull-up resistors can be connected in 3-bit units by using the pull-up resistor option register (PUO).
Page 77: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 This is an 8-bit I/O port with output latch. Port 4 can be specified in the input or output mode in 1-bit units by using port mode register 4 (PM4). When using P40 to P47 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using the pull-up resistor option register (PUO).
Page 78: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 This is a 4-bit I/O port with output latch. Port 5 can be specified in the input or output mode in 1-bit units by using the port mode register 5 (PM5). When using P50 to P53 pins as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using the pull-up resistor option register (PUO).
Page 79 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P51 PUO5 P-ch PORT Output Latch P51/TO2 (P51) PM51 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 5 read signal WR : Port 5 write signal User's Manual U11919EJ3V0UM00...
Page 80 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P52 and P53 PUO5 P-ch PORT Ouput Latch P52, P53 (P52, P53) PM52, PM53 PUO : Pull-up resistor option register PM : Port mode register : Port 5 read signal WR : Port 5 write signal User's Manual U11919EJ3V0UM00...
Page 81: Port Function Control Registers
CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0 to PM5) • Pull-up resistor option register (PUO) Port mode registers (PM0 to PM5) These registers are used to set port input/output in 1-bit units. Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.
Page 82 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Port Mode Register Format Symbol Address After Reset PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H PM22 PM21 PM20 FF22H PM32 PM31 PM30 FF23H PM47 PM46 PM45...
Page 83: Operation Of Port Functions
CHAPTER 4 PORT FUNCTIONS 4.4 Operation of Port Functions The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
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Page 85: Chapter 5 Clock Generation Circuit
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.1 Function of Clock Generation Circuit The clock generation circuit generates the clock to be supplied to the CPU and peripheral hardware. The system clock oscillator consists of the following type. • System clock oscillator This circuit oscillates at frequencies of 1.0 to 5.0 MHz.
Page 86: Register Controlling Clock Generation Circuit
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.3 Register Controlling Clock Generation Circuit The clock generation circuit is controlled by the following register: • Processor clock control register (PCC) Processor clock control register (PCC) PCC sets CPU clock selection and the ratio of division. PCC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 87: System Clock Oscillation Circuits
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.4 System Clock Oscillation Circuits 5.4.1 System clock oscillation circuit The system clock oscillation circuit is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the reversed signal to the X2 pin.
Page 88 CHAPTER 5 CLOCK GENERATION CIRCUIT Figure 5-4. Incorrect Examples of Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 5) User's Manual U11919EJ3V0UM00...
Page 89: Divider Circuit
CHAPTER 5 CLOCK GENERATION CIRCUIT Figure 5-4. Incorrect Examples of Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillation circuit (potential at points A, B, and C fluctuates) High Current (e) Signal is extracted 5.4.2 Divider circuit The divider circuit divides the output of the system clock oscillation circuit (f ) to generate various clocks.
Page 90: Operation Of Clock Generation Circuit
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.5 Operation of Clock Generation Circuit The clock generation circuit generates the following clocks and controls operation modes of the CPU, such as the standby mode: • System clock • CPU clock • Clock to peripheral hardware The operation of the clock generation circuit is determined by the processor clock control register (PCC), as follows: (1.6 µ...
Page 91: Changing Setting Of System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATION CIRCUIT 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 5-2).
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Page 93: Chapter 6 16-Bit Timer
CHAPTER 6 16-BIT TIMER 6.1 16-Bit Timer Functions 16-bit timer 20 has the following functions. • Timer interrupt • Timer output • Count value capture Timer interrupt An interrupt is generated when a count value and compare value matches. Timer output Timer output control is possible when a count value and compare value matches.
Page 94: 16-Bit Timer Configuration
CHAPTER 6 16-BIT TIMER 6.2 16-Bit Timer Configuration 16-bit timer 20 is configured in the following hardware. Table 6-1. Configuration of 16-Bit Timer 20 Item Configuration 16 bits × 1 (TM20) Timer counter Compare register : 16 bits × 1 (CR20) Register Capture register : 16 bits ×...
Page 95 CHAPTER 6 16-BIT TIMER 16-bit compare register 20 (CR20) This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and when they match, generates an interrupt request (INTTM2). CR20 is set with a 16-bit memory manipulation instruction. The 0000H to FFFFH values can be set. RESET input sets this register to FFFFH.
Page 96: Registers Controlling 16-Bit Timer
CHAPTER 6 16-BIT TIMER 6.3 Registers Controlling 16-Bit Timer The following two types of registers control 16-bit timer 20. • 16-bit timer mode control register 20 (TMC20) • Port mode register 5 (PM5) 16-bit timer mode control register 20 (TMC20) 16-bit timer mode control register 20 (TMC20) controls the setting of a count clock, capture edge, etc.
Page 97 CHAPTER 6 16-BIT TIMER Figure 6-2. 16-Bit Timer Mode Control Register 20 Format <6> <0> Symbol Address After Reset TMC20 TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 FF5BH Note TOD20 Timer Output Data Timer output data is 0. Timer output data is 1. TOF20 Overflow Flag Set Clear by reset and software...
Page 98 CHAPTER 6 16-BIT TIMER Port mode register 5 (PM5) This register sets the input/output of port 5 in 1-bit units. To use the P51/TO2 pin for timer output, set the output latch of PM51 and P51 to 0. PM5 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM5 to FFH.
Page 99: 16-Bit Timer Operation
CHAPTER 6 16-BIT TIMER 6.4 16-Bit Timer Operation 6.4.1 Operation as timer interrupt In the timer interrupt function, interrupts are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200. To operate the 16-bit timer as a timer interrupt, the following settings are required.
Page 100 CHAPTER 6 16-BIT TIMER Figure 6-5. Timer Interrupt Operation Timing Count Clock TM20 Count Value 0000H 0001H FFFFH 0000H 0001H FFFFH CR20 INTTM2 Interrupt Accepted Interrupt Accepted TO20 TOF20 Overflow Flag Set Remark N = 0000H to FFFFH User's Manual U11919EJ3V0UM00...
Page 101: Operation As Timer Output
CHAPTER 6 16-BIT TIMER 6.4.2 Operation as timer output Timer outputs are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance based on the intervals of the value set in TCL201 and TCL200. To operate the 16-bit timer as a timer output, the following settings are required. •...
Page 102: Capture Operation
CHAPTER 6 16-BIT TIMER 6.4.3 Capture operation The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) synchronizing with a capture trigger. Set as shown in Figure 6-8 to allow the 16-bit timer to start the capture operation. Figure 6-8.
Page 103: 16-Bit Timer Counter 20 Readout
CHAPTER 6 16-BIT TIMER 6.4.4 16-bit timer counter 20 readout The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction. TM20 readout is performed through a counter read buffer. The counter read buffer latches the TM20 count value.
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Page 105: Chapter 7 8-Bit Timer/Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.1 8-Bit Timer/Event Counter Functions 8-bit timer/event counter 00 (TM00) has the following functions: • Interval timer • External event counter • Square wave output 8-bit interval timer When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any time intervals set in advance.
Page 106: 8-Bit Timer/Event Counter Configuration
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counter consists of the following hardware configuration. Table 7-3. Configuration of 8-Bit Timer/Event Counter 00 Item Configuration 8 bits × 1 (TM00) Timer counter Compare register: 8 bits × 1 (CR00) Register Timer output 1 (TO0)
Page 107: 8-Bit Timer/Event Counter Control Registers
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.3 8-Bit Timer/Event Counter Control Registers The following two types of registers are used to control the 8-bit timer/event counter. • 8-bit timer mode control register 00 (TMC00) • Port mode register 5 (PM5) 8-bit timer mode control register 00 (TMC00) TMC00 determines whether to enable or disable 8-bit timer counter 00 (TM00), specifies the count clock for TM00, and controls the operation of the output control circuit of 8-bit timer/event counter 00.
Page 108 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Port mode register 5 (PM5) This register sets port 5 input/output in 1-bit units. When using the P50/TI0/TO0 pin for timer output, set PM50 and the output latch of P50 to 0. PM5 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM5 to FFH.
Page 109: 8-Bit Timer/Event Counter Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4 8-Bit Timer/Event Counter Operation 7.4.1 Operation as interval timer Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare register 00 (CR00) in advance. To operate the 8-bit timer/event counter as an interval timer, the following settings are required. <1>...
Page 110 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-4. Interval Timer Operation Timing Count Clock TM00 Count Value Clear Clear CR00 TCE00 Count Start INTTM0 Interrupt Accepted Interrupt Accepted Interval Time Interval Time Interval Time Interval time = (N + 1) × t Remark where N = 00H to FFH User's Manual U11919EJ3V0UM00...
Page 111: Operation As External Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI0/P50/TO0 pin by using timer counter 00 (TM00). To operate the 8-bit timer/event counter as an external event counter, the following settings are required. <1>...
Page 112: Operation As Square Wave Output
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.4.3 Operation as square wave output The 8-bit timer/event counter can generate the output square waves of arbitrary frequency at intervals specified by the count value set to 8-bit compare register 00 (CR00) in advance. To operate 8-bit timer/event counter 00 as square wave output, the following settings are required.
Page 113 CHAPTER 7 8-BIT TIMER/EVENT COUNTER Figure 7-6. Square Wave Output Timing Count Clock TM00 Count Value Clear Clear CR00 TCE00 Count Start INTTM0 Interrupt Accepted Interrupt Accepted Note Note The initial value of TO0 at output enable (TOE00 = 1) becomes low-level. User's Manual U11919EJ3V0UM00...
Page 114: Notes On Using 8-Bit Timer/Event Counters
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 7.5 Notes on Using 8-Bit Timer/Event Counters Error on starting timer An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated. This is because 8-bit timer counter 00 (TM00) started asynchronously with the count pulse. Figure 7-7.
Page 115: Chapter 8 Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.1 Watchdog Timer Functions The watchdog timer has the following functions: • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). Watchdog timer The watchdog timer is used to detect inadvertent program loops.
Page 116: Watchdog Timer Configuration
CHAPTER 8 WATCHDOG TIMER 8.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 8-1. Block Diagram of Watchdog Timer Internal Bus TMMK4 Prescaler...
Page 117: Watchdog Timer Control Registers
CHAPTER 8 WATCHDOG TIMER 8.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock.
Page 118 CHAPTER 8 WATCHDOG TIMER Watchdog timer mode register (WDTM) This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 8-3.
Page 119: Operation Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.4 Operation of Watchdog Timer 8.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).
Page 120: Operation As Interval Timer
CHAPTER 8 WATCHDOG TIMER 8.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1 respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value set in advance.
Page 121: Chapter 9 Serial Interface 00
CHAPTER 9 SERIAL INTERFACE 00 9.1 Serial Interface 00 Functions Serial interface 00 employs the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode Operation stop mode This mode is used when serial transfer is not carried out. It enables power consumption reduction. Asynchronous serial interface (UART) mode In this mode, one byte of data following the start bit is transmitted/received, and full-duplex operation is possible.
Page 122 CHAPTER 9 SERIAL INTERFACE 00 User's Manual U11919EJ3V0UM00...
Page 123 CHAPTER 9 SERIAL INTERFACE 00 User's Manual U11919EJ3V0UM00...
Page 124 CHAPTER 9 SERIAL INTERFACE 00 Transmit shift register 00 (TXS00) This register is used to specify data to be transmitted. Data written to TXS00 is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written to TXS00 are transferred as the transmit data.
Page 125: Serial Interface 00 Control Register
CHAPTER 9 SERIAL INTERFACE 00 9.3 Serial Interface 00 Control Register The following four types of registers are used to control serial interface 00. • Serial operation mode register 00 (CSIM00) • Asynchronous serial interface mode register 00 (ASIM00) • Asynchronous serial interface status register 00 (ASIS00) •...
Page 126 CHAPTER 9 SERIAL INTERFACE 00 Asynchronous serial interface mode register 00 (ASIM00) This register is set when using serial interface 00 in the asynchronous serial interface mode. ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. Figure 9-4.
Page 127 CHAPTER 9 SERIAL INTERFACE 00 Table 9-2. Serial Interface 00 Operating Mode Settings Operation stop mode ASIM00 CSIM00 PM22 PM21 PM20 P20 Start Shift P22/SI0/RxD P21/SO0/TxD P20/SCK0/ASCK Clock Pin Function Pin Function Pin Function TXE00 RXE00 CSIE00 DIR00 CSCK00 × ×...
Page 128 CHAPTER 9 SERIAL INTERFACE 00 Asynchronous serial interface status register 00 (ASIS00) This register indicates types of error when a reception error is generated in the asynchronous interface mode. ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS00 become undefined in the 3-wire serial I/O mode.
Page 129 CHAPTER 9 SERIAL INTERFACE 00 Baud rate generator control register 00 (BRGC00) This register is used to set the serial clock of serial interface 00. BRGC00 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC00 to 00H. Figure 9-6.
Page 130 CHAPTER 9 SERIAL INTERFACE 00 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of system clock The transmit/receive clock is generated by scaling the system clock.
Page 131 CHAPTER 9 SERIAL INTERFACE 00 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is found from the following expression. ASCK [Baud rate] = [Hz]...
Page 132: Serial Interface 00 Operation
CHAPTER 9 SERIAL INTERFACE 00 9.4 Serial Interface 00 Operation Serial interface 00 provides the following three types of modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 9.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed, therefore, the power consumption can be reduced. The P20/SCK0/ASCK, P21/SO0/TxD, and P22/SI0/RxD pins can be used as normal I/O ports.
Page 133 CHAPTER 9 SERIAL INTERFACE 00 (b) Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. Symbol <7> <6> Address After Reset ASIM00 TXE00 RXE00 PS001 PS000 CL00 SL00...
Page 134: Asynchronous Serial Interface (Uart) Mode
CHAPTER 9 SERIAL INTERFACE 00 9.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication is possible. This device incorporates a UART-dedicated baud rate generator that enables communications at a desired transfer rate from many options.
Page 135 CHAPTER 9 SERIAL INTERFACE 00 (b) Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. Symbol <7> <6> Address After Reset ASIM00 TXE00 RXE00 PS001 PS000 CL00 SL00...
Page 136 CHAPTER 9 SERIAL INTERFACE 00 (c) Asynchronous serial interface status register 00 (ASIS00) ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS00 to 00H. Symbol Address After Reset ASIS00 FE00 OVE00 FF71H PE00 PE00 Parity Error Flag Parity error not generated Parity error generated (when the parity of transmit data does not coincide.)
Page 137 CHAPTER 9 SERIAL INTERFACE 00 (d) Baud rate generator control register 00 (BRGC00) BRGC00 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC00 to 00H. Address After Reset Symbol BRGC00 TPS003 TPS002 TPS001 TPS000 FF73H TPS003 TPS002 TPS001 TPS000 3-Bit Counter Source Clock Selection...
Page 138 CHAPTER 9 SERIAL INTERFACE 00 Table 9-5. Example of Relationship between System Clock and Baud Rate Baud Rate (bps) BRGC00 Set Value Error (%) = 5.0 MHz = 4.9152 MHz 1,200 1.73 2,400 4,800 9,600 19,200 38,400 76,800 Caution Be sure not to select n = 1 during an operation at f = 5.0 MHz because n = 1 exceeds the baud rate limit.
Page 139 CHAPTER 9 SERIAL INTERFACE 00 Communication operation (a) Data format The transmit/receive data format is as shown in Figure 9-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length, parity selection, and specification of stop bit length for one data frame is carried out with asynchronous serial interface mode register 00 (ASIM00).
Page 140 CHAPTER 9 SERIAL INTERFACE 00 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 141 CHAPTER 9 SERIAL INTERFACE 00 (c) Transmission A transmit operation is started by writing transmit data to transmit shift register 00 (TXS00). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS00 is shifted out, and when TXS00 is empty, a transmission completion interrupt (INTST) is generated.
Page 142 CHAPTER 9 SERIAL INTERFACE 00 (d) Reception When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set to 1, a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM00. When the RxD pin input becomes low, the 3-bit counter starts counting, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output.
Page 143 CHAPTER 9 SERIAL INTERFACE 00 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, or overrun error. Upon data reception, an error flag is set in asynchronous serial interface status register 00 (ASIS00).
Page 144 CHAPTER 9 SERIAL INTERFACE 00 Cautions related to UART mode (a) When bit 7 (TXE00) of asynchronous serial interface mode register 00 (ASIM00) is cleared during transmission, be sure to set transmit shift register 00 (TXS00) to FFH, then set TXE00 to 1 before executing the next transmission.
Page 145: 3-Wire Serial I/O Mode
CHAPTER 9 SERIAL INTERFACE 00 9.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK0), serial output (SO0), and serial input (SI0).
Page 146 CHAPTER 9 SERIAL INTERFACE 00 (b) Asynchronous serial interface mode register 00 (ASIM00) ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM00 to 00H. When the 3-wire serial I/O mode is selected, 00H must be set to ASIM00. Symbol <7>...
Page 147 CHAPTER 9 SERIAL INTERFACE 00 (c) Baud rate generator control register 00 (BRGC00) BRGC00 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC00 to 00H. Address After Reset Symbol BRGC00 TPS003 TPS002 TPS001 TPS000 FF73H TPS003 TPS002 TPS001 TPS000 3-Bit Counter Source Clock Selection...
Page 148 CHAPTER 9 SERIAL INTERFACE 00 Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Transmit shift register 00 (TXS00/SIO00) and receive shift register 00 (RXS00) shift operations are performed in synchronization with the fall of the serial clock (SCK0).
Page 149: Chapter 10 Interrupt Functions
CHAPTER 10 INTERRUPT FUNCTIONS 10.1 Interrupt Function Types The following two types of interrupt functions are used. Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 150 CHAPTER 10 INTERRUPT FUNCTIONS Table 10-1. Interrupt Source List Note 1 Interrupt Type Priority Interrupt Source Internal/ Vector Basic External Table Configuration Name Trigger Note 2 Address Type − Non-maskable INTWDT Watchdog timer overflow (watchdog timer Internal 0004H mode 1 selected) Maskable INTWDT Watchdog timer overflow (interval timer...
Page 151 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal Bus Vector Table Interrupt Request Address Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus Vector Table Address Generator Interrupt Request Standby Release Signal (C) External maskable interrupt Internal Bus INTM0, KRM00...
Page 152: Interrupt Function Control Registers
CHAPTER 10 INTERRUPT FUNCTIONS 10.3 Interrupt Function Control Registers The following five registers are used to control the interrupt functions. • Interrupt request flag registers (IF0 and IF1) • Interrupt mask flag registers (MK0 and MK1) • External interrupt mode register 0 (INTM0) •...
Page 153 CHAPTER 10 INTERRUPT FUNCTIONS Interrupt request flag registers (IF0 and IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 upon acknowledgement of an interrupt request, upon RESET input, or when an instruction is executed.
Page 154 CHAPTER 10 INTERRUPT FUNCTIONS Interrupt mask flag registers (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 10-3.
Page 155 CHAPTER 10 INTERRUPT FUNCTIONS External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 10-4. External Interrupt Mode Register 0 Format Address After Reset Symbol...
Page 156 CHAPTER 10 INTERRUPT FUNCTIONS Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status of the interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped. Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI).
Page 157 CHAPTER 10 INTERRUPT FUNCTIONS Key return mode register 00 (KRM00) KRM00 is used to specify the pin at which a key return signal is detected. KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. Bit 0 (KRM000) is set for the four pins from KR0/P40 to KR3/P43. Bits 4 to 7 (KRM004 to KRM007) are set in 1-bit units for pins KR4/P44 to KR7/P47, respectively.
Page 158: Interrupt Processing Operation
CHAPTER 10 INTERRUPT FUNCTIONS 10.4 Interrupt Processing Operation 10.4.1 Non-maskable interrupt request acceptance operation The non-maskable interrupt request is unconditionally accepted even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Page 159 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-8. Flowchart from Non-Maskable Interrupt Request Generation to Acceptance Start WDTM4 = 1 (watchdog timer mode is selected) Interval Timer overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset Processing Interrupt request is generated Interrupt processing is started WDTM : Watchdog timer mode register : Watchdog timer Figure 10-9.
Page 160 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-10. Accepting Non-Maskable Interrupt Request Main Routine First Interrupt Processing NMI Request NMI Request (second) (first) Second Interrupt Processing User's Manual U11919EJ3V0UM00...
Page 161: Maskable Interrupt Request Acceptance Operation
CHAPTER 10 INTERRUPT FUNCTIONS 10.4.2 Maskable interrupt request acceptance operation A maskable interrupt request can be accepted when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is accepted in the interrupt enabled status (when the IE flag is set to 1).
Page 162 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-11. Interrupt Request Acceptance Program Algorithm Start ××IF = 1 ? Yes (Interrupt request generated) ××MK = 0 ? Interrupt Request Pending IE = 1 ? Interrupt Request Pending Vectored Interrupt Processing ××IF : Interrupt request flag ××MK : Interrupt mask flag : Flag to control maskable interrupt request acceptance (1 = enable, 0 = disable) User's Manual U11919EJ3V0UM00...
Page 163: Nesting Processing
CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-12. Interrupt Request Acceptance Timing (Example of MOV A,r) 8 Clocks Clock Saving PSW and PC, jump MOV A,r Interrupt Processing Program to interrupt processing Interrupt If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1, the interrupt is accepted after the instruction under execution completes.
Page 164 CHAPTER 10 INTERRUPT FUNCTIONS Figure 10-14. Example of Nesting Example 1. Nesting is accepted INTxx Processing INTyy Processing Main Processing IE = 0 IE = 0 INTxx INTyy RETI RETI During interrupt INTxx servicing, interrupt request INTyy is accepted, and a nesting is generated. An EI instruction is issued before each interrupt request acceptance, and the interrupt request acceptance enable state is set.
Page 165: Interrupt Request Reserve
CHAPTER 10 INTERRUPT FUNCTIONS 10.4.4 Interrupt request reserve Some instructions may reserve the acceptance of an interrupt request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution.
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Page 167: Chapter 11 Standby Function
CHAPTER 11 STANDBY FUNCTION 11.1 Standby Function and Configuration 11.1.1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes: HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.
Page 168: Standby Function Control Register
CHAPTER 11 STANDBY FUNCTION 11.1.2 Standby function control register The wait time after the STOP mode is released upon interrupt request until the oscillation settles is controlled with the oscillation settling time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 169: Operation Of Standby Function
CHAPTER 11 STANDBY FUNCTION 11.2 Operation of Standby Function 11.2.1 HALT mode HALT mode HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 11-1. HALT Mode Operating Status Item HALT Mode Operating Status Clock generation circuit...
Page 170 CHAPTER 11 STANDBY FUNCTION Releasing HALT mode The HALT mode can be released by the following three types of sources: (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is enabled to be accepted, vectored interrupt processing is performed.
Page 171 CHAPTER 11 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 11-3.
Page 172: Stop Mode
CHAPTER 11 STANDBY FUNCTION 11.2.2 STOP mode Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset.
Page 173 CHAPTER 11 STANDBY FUNCTION Releasing STOP mode The STOP mode can be released by the following two types of sources: (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled to be accepted, vectored interrupt processing is performed, after the oscillation settling time has elapsed.
Page 174 CHAPTER 11 STANDBY FUNCTION (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation settling time has elapsed. Figure 11-5. Releasing STOP Mode by RESET Input Wait STOP : 6.55 ms) Instruction...
Page 175: Chapter 12 Reset Function
CHAPTER 12 RESET FUNCTION The following two operations are available to generate reset signals. External reset input with RESET pin Internal reset by program run-away time detected with watchdog timer External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by reset signal input.
Page 176 CHAPTER 12 RESET FUNCTION Figure 12-2. Reset Timing by RESET Input Reset Period Oscillation Normal Operation Normal Operation (oscillation Settling (reset processing) stops) Time Wait RESET Internal Reset Signal Delay Delay Hi-Z Port Pin Figure 12-3. Reset Timing by Overflow in Watchdog Timer Reset Period Oscillation Normal Operation...
Page 177 CHAPTER 12 RESET FUNCTION Table 12-1. Hardware Status after Reset Hardware State after Reset Note 1 Program counter (PC) The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2...
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Page 179: Chapter 13 Μ Μ Μ Μ Pd78F9026A
CHAPTER 13 µ µ µ µ PD78F9026A The µ PD78F9026A is a version with an internal ROM of the mask ROM models replaced with a flash memory. The differences between the µ PD78F9026A and the mask ROM models are shown in Table 13-1. Table 13-1.
Page 180: Flash Memory Programming
CHAPTER 13 µ µ µ µ PD78F9026A 13.1 Flash Memory Programming The program memory provided to the µ PD78F9026A is flash memory. The flash memory can be written on-board, i.e., with the µ PD78F9026A mounted on the target system. To do so, connect a dedicated flash writer (Flashpro III (Part number: FL-PR3, PG-FP3)) to the host machine and target system.
Page 181: Flash Memory Programming Function
CHAPTER 13 µ µ µ µ PD78F9026A 13.1.2 Flash memory programming function An operation such as writing the flash memory is performed when a command or data is transmitted/received in the selected communication mode. The major flash memory programming functions are listed in Table 13-3. Table 13-3.
Page 182 CHAPTER 13 µ µ µ µ PD78F9026A Figure 13-3. Connection Example of Flashpro III in UART Mode µ PD78F9026A Flashpro III Note RESET RESET Note n = 1, 2 Figure 13-4. Connection Example of Flashpro III in Pseudo 3-Wire Mode (When using P0) µ...
Page 183: Setting Example When Using Flashpro Iii (Pg-Fp3)
CHAPTER 13 µ µ µ µ PD78F9026A 13.1.4 Setting example when using Flashpro III (PG-FP3) When writing data to flash memory by using Flashpro III (PG-FP3), set as follows. <1> Load the parameter file. <2> Select a serial mode and serial clock by using the type command. <3>...
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Page 185: Chapter 14 Instruction Set
CHAPTER 14 INSTRUCTION SET This chapter lists the instruction set of the µ PD789026 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User's Manual     Instruction (U11047E). 14.1 Operation 14.1.1 Operand identifiers and writing methods Operands are written in "Operand"...
Page 186: Description Of "Operation" Column
CHAPTER 14 INSTRUCTION SET 14.1.2 Description of "Operation" column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
Page 187: Operation List
CHAPTER 14 INSTRUCTION SET 14.2 Operation List Mnemonic Operands Byte Clock Operation Flag AC CY r ← byte r,#byte (saddr) ← byte saddr,#byte sfr ← byte sfr,#byte A ← r Note 1 r ← A Note 1 A ← (saddr) A,saddr (saddr) ←...
Page 188 CHAPTER 14 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag AC CY rp ← word MOVW rp,#word AX ← (saddrp) AX,saddrp (saddrp) ← AX saddrp,AX AX ← rp Note AX,rp rp ← AX Note rp,AX AX ↔ rp Note AX,rp XCHW A,CY ←...
Page 189 CHAPTER 14 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag AC CY A,CY ← A − byte − CY × × × SUBC A,#byte (saddr),CY ← (saddr) − byte − CY × × × saddr,#byte A,CY ← A − r − CY ×...
Page 190 CHAPTER 14 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag AC CY A − byte × × × A,#byte (saddr) − byte × × × saddr,#byte A − r × × × A − (saddr) × × × A,saddr A − (addr16) ×...
Page 191 CHAPTER 14 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag AC CY (SP−1) ← (PC+3) , (SP−2) ← (PC+3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP−1) ← (PC+1) , (SP−2) ← (PC+1) CALLT [addr5] ← (00000000,addr5+1), ←...
Page 192: Instructions Listed By Addressing Type
CHAPTER 14 INSTRUCTION SET 14.3 Instructions Listed by Addressing Type 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] $addr16 None [HL+byte] 1st Operand Note...
Page 193 CHAPTER 14 INSTRUCTION SET 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL. Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand...
Page 194 CHAPTER 14 INSTRUCTION SET Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic instructions CALL CALLT Compound instructions DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User's Manual U11919EJ3V0UM00...
Page 195: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the µ PD789026 Subseries. Figure A-1 shows development tools. • Compatibility with PC98-NX series Unless stated otherwise, products which are supported for the IBM PC/AT compatibles can also be used with the PC98-NX series.
Page 196 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Language Processing Software Embedded Software • Assembler package • OS • C compiler package • System simulator • Device file • C compiler source file • Integrated debugger Host Machine (PC or EWS) Interface adapter Flash Memory Writing Environment...
Page 197: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K0S Program that converts program written in mnemonic into object code that can be executed by Assembler package microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided.
Page 198: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS A.2 Flash Memory Writing Tools Flashpro III Flash writer dedicated to microcontrollers with flash memory. (part number: FL-PR3, PG-FP3) Flash writer FA-42CU Flash memory writing adapter. Used in connection with Flashpro III. • FA-42CU: For 42-pin plastic shrink DIP (CU type) FA-44GB •...
Page 199: Debugging Tools
APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware IE-78K0S-NS In-circuit emulator for debugging hardware and software upon developing the application In-circuit emulator system using 78K/0S series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine.
Page 200: Software
APPENDIX A DEVELOPMENT TOOLS A.3.2 Software ID78K0S-NS Control program for debugging 78K/0S Series. Integrated debugger This program provides a graphical user interface. It runs on Windows for personal computer (Supports in-circuit emulator users and on OSF/Motif for engineering work station users, and has visual designs and IE78K0S-NS) operationability that comply with these operating systems.
Page 201: Conversion Socket (Ev-9200G-44) Drawing And Recommended Footprint
APPENDIX A DEVELOPMENT TOOLS A.4 Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint Figure A-2. EV-9200G-44 Package Drawing (Reference) Based on EV-9200G-44 (1) Package drawing (in mm) EV-9200G-44 No.1 pin index EV-9200G-44-G0 ITEM MILLIMETERS INCHES 15.0 0.591 10.3 0.406 10.3 0.406 15.0 0.591 4-C 3.0...
Page 202 APPENDIX A DEVELOPMENT TOOLS Figure A-3. EV-9200G-44 Recommended Footprint (Reference) Based on EV-9200G-44 (2) Pad drawing (in mm) EV-9200G-44-P1E ITEM MILLIMETERS INCHES 15.7 0.618 11.0 0.433 0.8 ± 0.02 × 10=8.0 ± 0.05 × 0.394=0.315 +0.002 +0.002 0.031 –0.001 –0.002 0.8 ±...
Page 203: Conversion Adapter (Tgb-044Sap) Drawing
APPENDIX A DEVELOPMENT TOOLS A.5 Conversion Adapter (TGB-044SAP) Drawing Figure A-4. TGB-044SAP Package Drawing (Reference) Reference diagram: TGB-044SAP (TQPACK044SA+TQSOCKET044SAP) Package dimension (unit: mm) Protrusion height ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES 10.12 0.398 0.079 0.8x10=8.0 0.031x0.394=0.315 0.25 0.010 0.031 0.378 16.65 0.656 0.047...
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Page 205: Appendix B Embedded Software
APPENDIX B EMBEDDED SOFTWARE The following embedded software products are available for efficient program development and maintenance of the µ PD789026 Subseries. MX78K0S is a subset OS that is based on the µ ITRON specification. Supplied with the MX78K0S MX78K0S nucleus. The MX78K0S OS controls tasks, events, and time. In task control, the MX78K0S OS controls task execution order, and performs the switching process to a task to be executed.
Page 206 [MEMO] User's Manual U11919EJ3V0UM00...
Page 207: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Name Index 16-bit capture register 20 (TCP20)..........................95 16-bit compare register 20 (CR20)..........................95 16-bit timer counter 20 (TM20)............................ 95 16-bit timer mode control register 20 (TMC20) ......................96 8-bit compare register 00 (CR00)..........................106 8-bit timer counter 00 (TM00)............................
Page 208 APPENDIX C REGISTER INDEX Port mode register 3 (PM3)............................81 Port mode register 4 (PM4)............................81 Port mode register 5 (PM5)..........................81, 98, 108 Processor clock control register (PCC) ........................86 Pull-up resistor option register (PUO) ..........................82 Receive buffer register 00 (RXB00) ...........................124 Receive shift register 00 (RXS00)..........................124 Serial operation mode register 00 (CSIM00)..................125, 132, 134, 145 Timer clock select register 2 (TCL2) ..........................117 Transmit shift register 00 (TXS00) ..........................124...
Page 209: Register Symbol Index
APPENDIX C REGISTER INDEX C.2 Register Symbol Index ASIM00 : Asynchronous serial interface mode register 00 ............126, 133, 135, 146 ASIS00 : Asynchronous serial interface status register 00 ................128, 136 BRGC00 : Baud rate generator control register 00 ................. 129, 137, 147 CR00 : 8-bit compare register 00 ........................
Page 210 APPENDIX C REGISTER INDEX TCL2 : Timer clock select register 2 ........................117 TCP20 : 16-bit capture register 20 .........................95 TM00 : 8-bit timer counter 00 ..........................106 TM20 : 16-bit timer counter 20 ..........................95 TMC00 : 8-bit timer mode control register 00 .......................107 TMC20 : 16-bit timer mode control register 20 .......................96 TXS00...
Page 211: Appendix D Revision History
APPENDIX D REVISION HISTORY Here is the revision history of this manual. "Chapter" indicates the chapter of the previous edition. Edition Revision from Previous Edition Chapter Change of µ PD789025 and µ PD789026 from "under development" to Second edition Throughout "developed"...
Page 212 [MEMO] User's Manual U11919EJ3V0UM00...
Page 213 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

This manual is also suitable for:

Mpd789022 Mpd789024 Mpd789025Mpd789026Mpd78f9026a

NEC mPD789026 Subseries User Manual

Section 1

Section 2

Chapter 1 General

Features

Applications

Ordering Information

Pin Configuration (Top View)

Development of 78K/0S Series

Block Diagram

Outline of Functions

Chapter 2 Pin Functions

List of Pin Functions

Description of Pin Functions

Pin Input/Output Circuits and Connection of Unused Pins

Chapter 3 Cpu Architecture

Memory Space

Processor Registers

Instruction Address Addressing

Operand Address Addressing

Chapter 4 Port Functions

Functions of Ports

Port Configuration

Port Function Control Registers

Operation of Port Functions

Function of Clock Generation Circuit

Configuration of Clock Generation Circuit

Chapter 5 Clock Generation Circuit

Register Controlling Clock Generation Circuit

System Clock Oscillation Circuits

Operation of Clock Generation Circuit

Changing Setting of System Clock and CPU Clock

Chapter 6 16-Bit Timer

16-Bit Timer Functions

16-Bit Timer Configuration

Registers Controlling 16-Bit Timer

16-Bit Timer Operation

8-Bit Timer/Event Counter Functions

Chapter 7 8-Bit Timer/Event Counter

8-Bit Timer/Event Counter Configuration

8-Bit Timer/Event Counter Control Registers

8-Bit Timer/Event Counter Operation

Notes on Using 8-Bit Timer/Event Counters

Chapter 8 Watchdog Timer

Watchdog Timer Functions

Watchdog Timer Configuration

Watchdog Timer Control Registers

Operation of Watchdog Timer

Chapter 9 Serial Interface 00

Serial Interface 00 Functions

Serial Interface 00 Configuration

Serial Interface 00 Control Register

Serial Interface 00 Operation

Chapter 10 Interrupt Functions

Interrupt Function Types

Interrupt Sources and Configuration

Interrupt Function Control Registers

Interrupt Processing Operation

Chapter 11 Standby Function

Standby Function and Configuration

Operation of Standby Function

Chapter 12 Reset Function

CHAPTER 13 Μ Μ Μ Μ PD78F9026A

Flash Memory Programming

Chapter 14 Instruction Set

Operation

Operation List

Instructions Listed by Addressing Type

Appendix A Development Tools

Language Processing Software

Flash Memory Writing Tools

Debugging Tools

Conversion Socket (EV-9200G-44) Drawing and Recommended Footprint

Conversion Adapter (TGB-044SAP) Drawing

Appendix B Embedded Software

Appendix C Register Index

Register Name Index

Register Symbol Index

Appendix D Revision History

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