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3.2 Processor Registers
78K0/KB1+ products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
15
PC
PC15 PC14 PC13 PC12 PC11 PC10 PC9
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are reset upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
PSW
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledgment operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and maskable interrupt requests are all
disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment enable is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
CHAPTER 3 CPU ARCHITECTURE
Figure 3-7. Format of Program Counter
PC8
Figure 3-8. Format of Program Status Word
7
IE
Z
RBS1
AC
Preliminary User's Manual U16846EJ1V0UD
PC7
PC6
PC5
PC4
PC3
0
RBS0
0
ISP
CY
0
PC2
PC1 PC0
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