Page 1 Preliminary User’s Manual 78K0/KB1+ 8-Bit Single-Chip Microcontrollers µ PD78F0101H µ PD78F0102H µ PD78F0103H Document No. U16846EJ1V0UD00 (1st edition) Date Published November 2003 N CP(K) 2003 Printed in Japan...
Page 2 [MEMO] Preliminary User’s Manual U16846EJ1V0UD...
Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KB1+ and design and develop application systems and programs for these devices. The target products are as follows. µ 78K0/KB1+: PD78F0101H, 78F0102H, 78F0103H Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...
Page 8 Document No. SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ..........................15 Features ............................15 Applications..........................16 Ordering Information ......................... 16 Pin Configuration (Top View)....................17 K1 Family Lineup ........................18 1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup ....................18 1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup ..................21 Block Diagram ..........................24 Outline of Functions ........................
Page 10 Operand Address Addressing ....................55 3.4.1 Implied addressing .......................... 55 3.4.2 Register addressing ........................56 3.4.3 Direct addressing ..........................57 3.4.4 Short direct addressing ........................58 3.4.5 Special function register (SFR) addressing ..................59 3.4.6 Register indirect addressing ......................60 3.4.7 Based addressing..........................
Page 11 6.4.2 PPG output operations........................118 6.4.3 Pulse width measurement operations ....................121 6.4.4 External event counter operation ....................129 6.4.5 Square-wave output operation .......................132 6.4.6 One-shot pulse output operation ....................134 Cautions for 16-Bit Timer/Event Counter 00 ................. 139 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50................142 Functions of 8-Bit Timer/Event Counter 50................
Page 12 10.6 Cautions for A/D Converter..................... 197 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) ..... 202 11.1 Functions of Serial Interface UART0..................202 11.2 Configuration of Serial Interface UART0 ................203 11.3 Registers Controlling Serial Interface UART0............... 206 11.4 Operation of Serial Interface UART0 ..................
Page 13 CHAPTER 17 CLOCK MONITOR ......................311 17.1 Functions of Clock Monitor ....................311 17.2 Configuration of Clock Monitor ....................311 17.3 Register Controlling Clock Monitor ..................312 17.4 Operation of Clock Monitor..................... 313 CHAPTER 18 POWER-ON-CLEAR CIRCUIT ..................318 18.1 Functions of Power-on-Clear Circuit ..................318 18.2 Configuration of Power-on-Clear Circuit................
Page 14 22.1.2 Description of operation column .....................359 22.1.3 Description of flag operation column ....................359 22.2 Operation List ........................... 360 22.3 Instructions Listed by Addressing Type................368 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET)............... 371 CHAPTER 24 PACKAGE DRAWING....................384 CHAPTER 25 CAUTIONS FOR WAIT....................385 25.1 Cautions for Wait........................
Page 15: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features µ Minimum instruction execution time can be changed from high speed (0.125 s: @ 16 MHz operation with high- µ speed system clock) to low-speed (2.0 s: @ 16 MHz operation with high-speed system clock) General-purpose register: 8 bits ×...
Page 16: Applications
CHAPTER 1 OUTLINE 1.2 Applications Automotive equipment • System control for body electricals (power windows, keyless entry reception, etc.) • Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances • Outdoor air conditioner units •...
Page 17: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 30-pin plastic SSOP (7.62 mm (300)) P33/INTP4 P120/INTP0 P32/INTP3 P31/INTP2 P30/INTP1 P20/ANI0 FLMD0 P21/ANI1 P22/ANI2 P23/ANI3 X1[CL1] P130 X2[CL2] P17/TI50/TO50/FLMD1 RESET P16/TOH1/INTP5 P15/TOH0 P14/RxD6 P01/TI010/TO00 P13/TxD6 P00/TI000 P12/SO10 Note Note P10/SCK10/TxD0 P11/SI10/RxD0 µ...
Page 18: K1 Family Lineup
CHAPTER 1 OUTLINE 1.5 K1 Family Lineup 1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup • 30-pin SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 78K0/KB1+ µ µ µ PD78F0103 PD780103 PD78F0103H Mask ROM: 24 KB, Single-power-supply flash memory: 24 KB, Two-power-supply flash memory: 24 KB, RAM: 768 B RAM: 768 B RAM: 768 B...
Page 19 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1+ 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins − − − − 48 K/ −...
Page 20 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1+ is shown below. Part Number 78K0/KB1+ 78K0/KC1+ 78K0/KD1+ 78K0/KE1+ 78K0/KF1+ Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins Internal Flash memory 8 K 16 K/24 K 16 K 24 K/32 K 16 K 24 K/32 K 16 K 24 K/32 K 48 K/60 K 60 K memory (bytes)
Page 21: V850Es/Kx1, V850Es/Kx1+ Product Lineup
CHAPTER 1 OUTLINE 1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup 64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch) • 64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch) • 64-pin plastic LQFP (14 × 14 mm, 0.8 mm pitch) •...
Page 22 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Part Number V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1 Item Number of pins 64 pins 80 pins 100 pins 144 pins − − − − − − − Internal Mask ROM 96/128 memory −...
Page 23 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1+ is shown below. Part Number V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+ Item Number of pins 64 pins 80 pins 100 pins 144 pins − − − − Internal Mask ROM 96/128 128/256 128/256 memory −...
Page 24: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 16-bit timer/ Port 0 P00 to P03 event counter 00 TI000/P00 Port 1 P10 to P17 8-bit timer H0 TOH0/P15 Port 2 P20 to P23 TOH1/P16 Port 3 8-bit timer H1 P30 to P33 Port 12 P120 78K/0...
Page 25: Outline Of Functions
CHAPTER 1 OUTLINE 1.7 Outline of Functions µ µ µ Item PD78F0101H PD78F0102H PD78F0103H Internal memory Flash memory 8 KB 16 KB 24 KB (self-programming supported) High-speed RAM 512 bytes 768 bytes Memory space 64 KB • Ceramic/crystal/external clock oscillation High-speed system clock (oscillation frequency) (2 to 16 MHz: V...
Page 26 CHAPTER 1 OUTLINE An outline of the timer is shown below. 16-Bit Timer/Event 8-Bit Timer/Event 8-Bit Timers H0 and H1 Watchdog Timer Counter 00 Counter 50 TMH0 TMH1 Operation Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel mode −...
Page 27: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are two types of pin I/O buffer power supplies: AV and V . The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P23...
Page 28 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising Input P120 edge, falling edge, or both rising and falling edges) can be INTP1 to INTP4 P30 to P33 specified INTP5...
Page 29: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (port 0) P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P03 function as a 4-bit I/O port.
Page 30: P20 To P23 (Port 2)
CHAPTER 2 PIN FUNCTIONS Note (e) TxD0 , TxD6 These are serial data output pins of the asynchronous serial interface. µ Note TxD0 and RxD0 are available only in the PD78F0102H and 78F0103H. (f) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (g) TO50, TOH0, and TOH1 These are timer output pins.
Page 31: P130 (Port 13)
CHAPTER 2 PIN FUNCTIONS (2) Control mode P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.6 P130 (port 13) P130 functions as a 1-bit output-only port. 2.2.7 AV This is the A/D converter reference voltage input pin.
Page 32: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuit and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuits of each type. Table 2-2.
Page 33 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List Type 2 Type 8-A Pull-up P-ch enable Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output N-ch disable Type 3-C Type 9-C Comparator P-ch N-ch P-ch – Data (threshold voltage) N-ch Input enable...
Page 34: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KB1+ can each access a 64 KB memory space. Figures 3-1 to 3-3 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of internal memory size switching register (IMS) of all products in the 78K0/KB1+ are fixed (IMS = CFH).
Page 35 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-1. Memory Map ( PD78F0101H) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 512 × 8 bits Program area Data memory space CALLF entry area Reserved Program area Option byte area...
Page 36 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD78F0102H) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 768 × 8 bits Program area Data memory space CALLF entry area Reserved Program area Option byte area...
Page 37 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-3. Memory Map ( PD78F0103H) Special function registers (SFR) 256 × 8 bits General-purpose registers 32 × 8 bits Internal high-speed RAM 768 × 8 bits Program area Data memory space CALLF entry area Reserved Program area Option byte area...
Page 38: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KB1+ products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure...
Page 39: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 78K0/KB1+ products incorporate the following internal high-speed RAM. Table 3-4. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM µ 512 × 8 bits (FD00H to FEFFH) PD78F0101H µ 768 × 8 bits (FC00H to FEFFH) PD78F0102H µ...
Page 40: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KB1+, based on operability and other considerations.
Page 41 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-5. Correspondence Between Data Memory and Addressing ( PD78F0102H) Special function registers (SFR) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 768 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 42 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-6. Correspondence Between Data Memory and Addressing ( PD78F0103H) Special function registers (SFR) SFR addressing 256 × 8 bits General-purpose registers Register addressing 32 × 8 bits Short direct addressing Internal high-speed RAM 768 × 8 bits Direct addressing Register indirect addressing Based addressing...
Page 43: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers 78K0/KB1+ products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 44 CHAPTER 3 CPU ARCHITECTURE (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
Page 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair upper FEDEH FEDEH Register pair lower (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
Page 46 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair upper FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15-PC8...
Page 47: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 48: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions.
Page 49 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √ √ − FF01H Port register 1 √...
Page 50 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF50H Asynchronous serial interface operation mode ASIM6 register 6 −...
Page 51 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (3/3) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FFBCH Capture/compare control register 00 CRC00 √ √ −...
Page 52: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 53: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 54: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 55: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed.
Page 56: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 57: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...
Page 58: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 59: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 60: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces.
Page 61: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 62: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 63: Stack Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
Page 64: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AV and V . The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P23...
Page 65: Port Configuration
CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions Pin Name Function After Reset Alternate Function Port 0. Input TI000 4-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. − Use of an on-chip pull-up resistor can be specified by a software setting.
Page 66: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 67 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P01 PU01 P-ch Alternate function PORT Output latch P01/TI010/TO00 (P01) PM01 Alternate function PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal Preliminary User’s Manual U16846EJ1V0UD...
Page 68 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P02 and P03 PU02, PU03 P-ch PORT Output latch P02, P03 (P02, P03) PM02, PM03 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal Preliminary User’s Manual U16846EJ1V0UD...
Page 69: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Page 70 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch Note P11/SI10 (/RxD0 (P11, P14) P14/RxD6 PM11, PM14 µ Note Available only in the PD78F0102H and 78F0103H. PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal...
Page 71 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P12 and P15 PU12, PU15 P-ch PORT Output latch (P12, P15) P12/SO10, P15/TOH0 PM12, PM15 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U16846EJ1V0UD...
Page 72 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P13 PU13 P-ch PORT Output latch (P13) P13/TxD6 PM13 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U16846EJ1V0UD...
Page 73 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1/INTP5, (P16, P17) P17/TI50/TO50/FLMD1 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U16846EJ1V0UD...
Page 74: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is a 4-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-10 shows a block diagram of port 2. Figure 4-10. Block Diagram of P20 to P23 A/D converter P20/ANI0 to P23/ANI3 Read signal...
Page 75: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
Page 76: Port 12
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 12 Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When the P120 pin is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 77: Port 13
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 13 Port 13 is a 1-bit output-only port. Figure 4-13 shows a block diagram of port 13. Figure 4-13. Block Diagram of P130 PORT Output latch P130 (P130) Read signal WR××: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.
Page 78 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Mode Register Symbol Address After reset PM03 PM02 PM01 PM00 FF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H PM33 PM32 PM31 PM30 FF23H PM12 PM120 FF2CH PMmn Pmn pin I/O mode selection (m = 0, 1, 3, 12;...
Page 79 CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0 to P3, P12, P13) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
Page 80 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3, and PU12) These registers specify whether the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P33, or P120 is to be used or not. An on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified.
Page 81: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit.
Page 82: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two system clock oscillators are available. • High-speed system clock oscillator The following two high-speed system clock oscillators are available. Crystal/ceramic oscillator: Oscillates a clock of f = 2 to 16 MHz •...
Page 83 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus Oscillation Processor clock Main clock Main OSC stabilization time mode register control register control register select register (PCC) (MOC) (MCM) (OSTS) OSTS2 OSTS1 OSTS0 PCC2 PCC1 PCC0 MSTOP MCM0 STOP...
Page 84: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator. • Processor clock control register (PCC) • Ring-OSC mode register (RCM) • Main clock mode register (MCM) • Main OSC control register (MOC) •...
Page 85 CHAPTER 5 CLOCK GENERATOR The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KB1+. Therefore, the relationship between the CPU clock (f ) and minimum instruction execution time is as shown in the Table 5-2. Table 5-2.
Page 86 CHAPTER 5 CLOCK GENERATOR (3) Main clock mode register (MCM) This register sets the CPU clock (high-speed system clock/Ring-OSC clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-4. Format of Main Clock Mode Register (MCM) Note Address: FFA1H After reset: 00H...
Page 87 CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the high-speed system clock oscillator operation when the CPU is operating with the Ring-OSC clock.
Page 88 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H Symbol OSTC MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status = 10 MHz f = 16 MHz µ...
Page 89 CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time select register (OSTS) This register is used to select the oscillation stabilization wait time of the high-speed system clock when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the high-speed system clock selected as the CPU clock.
Page 90 CHAPTER 5 CLOCK GENERATOR (7) System wait control register (VSWC) This register is used to control wait states when a high-speed CPU and a low-speed peripheral I/O are connected. VSWC can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 91: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 High-speed system clock oscillator The following two high-speed system clock oscillators are available. • Crystal/ceramic oscillator: Oscillates a clock of f = 2 to 16 MHz • External RC oscillator: Oscillates a clock of f = 3 to 4 MHz High-speed system clock oscillation can be selected using the option byte.
Page 92 CHAPTER 5 CLOCK GENERATOR Figure 5-10. Examples of Incorrect Resonator Connection (a) Too long wiring (b) Crossed signal line PORT (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Preliminary User’s Manual U16846EJ1V0UD...
Page 93 CHAPTER 5 CLOCK GENERATOR (2) External RC oscillator The external RC oscillator is oscillated by the resistor (R) and capacitor (C) connected across the CL1 and CL2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the CL1 pin, and input the inverted signal to the CL2 pin.
Page 94 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Example of Incorrect Resonator Connection (a) Too long wiring (b) Crossed signal line PORT (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A and B fluctuates) PORT High current High current...
Page 95: Ring-Osc Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.2 Ring-OSC oscillator A Ring-OSC oscillator is incorporated in the 78K0/KB1+. “Can be stopped by software” or “Cannot be stopped” can be selected by the option byte. The Ring-OSC clock always oscillates after RESET release (240 kHz (TYP.)). 5.4.3 Prescaler The prescaler generates various clocks by dividing the high-speed system clock oscillator output when the high- speed system clock is selected as the clock to be supplied to the CPU.
Page 96 CHAPTER 5 CLOCK GENERATOR (2) Improvement of performance Because the CPU can be started without waiting for the high-speed system clock oscillation stabilization time, the total performance can be improved. A timing diagram of the CPU default start using Ring-OSC is shown in Figure 5-13. Figure 5-13.
Page 97 CHAPTER 5 CLOCK GENERATOR A status transition diagram of this product is shown in Figure 5-14, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 5-3 and 5-4, respectively.
Page 98 CHAPTER 5 CLOCK GENERATOR Figure 5-14. Status Transition Diagram (2/2) (2) When “Ring-OSC cannot be stopped” is selected by option byte HALT HALT HALT instruction Interrupt Interrupt instruction Interrupt HALT instruction Status 3 Status 2 Status 1 Note 2 MCM0 = 0 MSTOP = 1 CPU clock: f CPU clock: f...
Page 99 CHAPTER 5 CLOCK GENERATOR Table 5-3. Relationship Between Operation Clocks in Each Operation Status Status High-Speed Ring-OSC Oscillator CPU Clock Prescaler Clock Supplied to System Clock After Peripherals Oscillator Release Note 1 Note 2 MCM0 = 0 MCM0 = 1 Operation RSTOP = 0 RSTOP = 1...
Page 100: Time Required To Switch Between Ring-Osc Clock And High-Speed System Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Time Required to Switch Between Ring-OSC Clock and High-Speed System Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and high- speed system clock. In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions are executed using the pre-switch over clock after switching MCM0 (see Table 5-5).
Page 101: Clock Switching Flowchart And Register Setting
CHAPTER 5 CLOCK GENERATOR 5.8 Clock Switching Flowchart and Register Setting 5.8.1 Switching from Ring-OSC clock to high-speed system clock Figure 5-15. Switching from Ring-OSC Clock to High-Speed System Clock (Flowchart) After reset release PCC = 00H RCM = 00H ;...
Page 102: Switching From High-Speed System Clock To Ring-Osc Clock
CHAPTER 5 CLOCK GENERATOR 5.8.2 Switching from high-speed system clock to Ring-OSC clock Figure 5-16. Switching from High-Speed System Clock to Ring-OSC Clock (Flowchart) Register setting ; High-speed system clock operation MCM = 03H in high-speed system clock operation Yes: RSTOP = 1 High-speed system Note RCM.0...
Page 103: Register Settings
CHAPTER 5 CLOCK GENERATOR 5.8.3 Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. Table 5-7. Clock and Register Settings Mode Setting Flag Status Flag MCM Register MOC Register RCM Register MCM Register Note 1...
Page 104: Chapter 6 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. • Interval timer • PPG output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
Page 105: Configuration Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Timer counter 16 bits (TM00) Register 16-bit timer capture/compare register: 16 bits (CR000, CR010) Timer input TI000, TI010 Timer output...
Page 106 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00) Address: FF10H, FF11H After reset: 0000H Symbol...
Page 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES001 ES000 Falling edge...
Page 108 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer capture/compare register 010 (CR010) CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00).
Page 109: Registers Controlling 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 The following six registers are used to control 16-bit timer/event counter 00. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register 00 (CRC00) • 16-bit timer output control register 00 (TOC00) •...
Page 110 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 inversion timing Interrupt request mode selection selection generation...
Page 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC00 to 00H. Figure 6-6.
Page 112 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter 00 output controller. It sets/resets the timer output F/F (LV00), enables/disables output inversion and 16-bit timer/event counter 00 timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software.
Page 113 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the valid edges of the TI000 and TI010 pin input. PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM00 to 00H.
Page 114 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 00 is not guaranteed.
Page 115: Operation Of 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.
Page 116 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000...
Page 117 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-11. Interval Timer Configuration Diagram 16-bit timer capture/compare register 000 (CR000) INTTM000 16-bit timer counter 00 Note OVF00 (TM00) Noise TI000/P00 eliminator Clear circuit Note OVF00 is set to 1 only when CR000 is set to FFFFH. Figure 6-12.
Page 118: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-13 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1>...
Page 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-13. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000...
Page 120 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Configuration of PPG Output 16-bit timer capture/compare register 000 (CR000) Clear 16-bit timer counter 00 circuit (TM00) Noise TI000/P00 eliminator TO00/TI010/P01 16-bit timer capture/compare register 010 (CR010) Figure 6-15. PPG Output Operation Timing Count clock M −...
Page 121: Pulse Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
Page 122 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set.
Page 123 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter 16-bit timer counter 00 OVF00 (TM00) 16-bit timer capture/compare TI000 register 010 (CR010) INTTM010 Internal bus Figure 6-19. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock 0000H...
Page 124 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 125 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM00 count value TI000 pin input CR010 capture value INTTM010...
Page 126 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. When the rising or falling edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set.
Page 127 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM00 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI000 pin input CR010 capture value...
Page 128 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001...
Page 129: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-26 for the set value). <2> Set the count clock by using the PRM00 register. <3>...
Page 130 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-26. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001...
Page 131 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear Noise eliminator Note OVF00 16-bit timer counter 00 (TM00) Valid edge of TI000 pin Note OVF00 is set to 1 only when CR000 is set to FFFFH. Figure 6-28.
Page 132: Square-Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-29 for the set value). <3>...
Page 133 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 TOC00 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting “11”...
Page 134: One-Shot Pulse Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1>...
Page 135 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Free-running mode (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 as compare register CR010 as compare register...
Page 136 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 0CH (TM00 count starts) Count clock TM00 count 0000H 0001H N + 1 0000H N – 1 M – 1 M + 1 M + 2 CR010 set value CR000 set value...
Page 137 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 TMC00 Clears and starts at valid edge of TI000 pin (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00...
Page 138 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) Count clock M − 2 M − 1 TM00 count value 0000H 0001H 0000H...
Page 139: Cautions For 16-Bit Timer/Event Counter 00
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions for 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Page 140 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (6) Operation of OVF00 flag <1> The OVF00 flag is also set to 1 in the following case. When of the following modes: the mode in which clear & start occurs on a match between TM00 and CR000, the mode in which clear &...
Page 141 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (8) Timer operation <1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010). <2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins are not acknowledged.
Page 142: Chapter 7 8-Bit Timer/Event Counter 50
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.1 Functions of 8-Bit Timer/Event Counter 50 8-bit timer/event counter 50 has the following functions. • Interval timer • External event counter • Square-wave output • PWM output Figure 7-1 shows the block diagram of 8-bit timer/event counter 50. Figure 7-1.
Page 143: Configuration Of 8-Bit Timer/Event Counter 50
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.2 Configuration of 8-Bit Timer/Event Counter 50 8-bit timer/event counter 50 includes the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counter 50 Item Configuration Timer register 8-bit timer counter 50 (TM50) Register 8-bit timer compare register 50 (CR50) Timer input TI50 Timer output...
Page 144 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 (2) 8-bit timer compare register 50 (CR50) CR50 can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR50 is constantly compared with the 8-bit timer counter 50 (TM50) count value, and an interrupt request (INTTM50) is generated if they match.
Page 145: Registers Controlling 8-Bit Timer/Event Counter 50
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.3 Registers Controlling 8-Bit Timer/Event Counter 50 The following four registers are used to control 8-bit timer/event counter 50. • Timer four selection register 50 (TCL50) • 8-bit timer mode control register 50 (TMC50) •...
Page 146 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 (2) 8-bit timer mode control register 50 (TMC50) TMC50 is a register that performs the following five types of settings. <1> 8-bit timer counter 50 (TM50) count operation control <2> 8-bit timer counter 50 (TM50) operating mode selection <3>...
Page 147 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 Cautions 1. The settings of LVS50 and LVR50 are valid in other than PWM mode. 2. Do not make settings <1> to <4> below simultaneously. In addition, follow the setting procedure shown below. <1> Setting of TMC501 and TMC506: Setting of operation mode <2>...
Page 148: Operations Of 8-Bit Timer/Event Counter 50
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.4 Operations of 8-Bit Timer/Event Counter 50 7.4.1 Operation as interval timer 8-bit timer/event counter 50 operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 50 (CR50). When the count value of 8-bit timer counter 50 (TM50) matches the value set to CR50, counting continues with the TM50 value cleared to 0 and an interrupt request signal (INTTM50) is generated.
Page 149 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 Figure 7-7. Interval Timer Operation Timing (2/2) (b) When CR50 = 00H Count clock TM50 CR50 TCE50 INTTM50 Interval time (c) When CR50 = FFH Count clock TM50 FEH FFH 00H CR50 TCE50 INTTM50 Interrupt acknowledged Interrupt acknowledged...
Page 150: Operation As External Event Counter
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI50 pin by 8-bit timer counter 50 (TM50). TM50 is incremented each time the valid edge specified by timer clock selection register 50 (TCL50) is input. Either the rising or falling edge can be selected.
Page 151: Operation As Square-Wave Output
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.4.3 Operation as square-wave output A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 50 (CR50). The TO50 pin output status is inverted at intervals determined by the count value preset to CR50 by setting bit 0 (TOE50) of 8-bit timer mode control register 50 (TMC50) to 1.
Page 152: Operation As Pwm Output
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 7.4.4 Operation as PWM output 8-bit timer/event counter 50 operates as a PWM output when bit 6 (TMC506) of 8-bit timer mode control register 50 (TMC50) is set to 1. The duty pulse is determined by the value set to 8-bit timer compare register 50 (CR50). Set the active level width of the PWM pulse to CR50;...
Page 153 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 Figure 7-10. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM50 00H 01H FFH 00H 01H 02H N N+1 FFH 00H 01H 02H CR50 TCE50 INTTM50 TO50 <1> <5> <2>...
Page 154: Cautions For 8-Bit Timer/Event Counter 50
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50 (2) Operation with CR50 changed Figure 7-11. Timing of Operation with CR50 Changed (a) CR50 value is changed from N to M before clock rising edge of FFH → Value is transferred to CR50 at overflow immediately after change. Count clock TM50 N N + 1 N + 2...
Page 155: Chapter 8 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • Interval timer • PWM output mode • Square-wave output 8.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware.
Page 156 Figure 8-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) 8-bit timer H 8-bit timer H TMHE0 CKS02 CKS01 CKS00 TMMD01TMMD00 TOLEV0 TOEN0 compare register compare register 10 (CMP10) 00 (CMP00) TOH0/P15 Decoder Selector Output latch PM15...
Page 157 Figure 8-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) 8-bit timer H 8-bit timer H TMHE1 CKS12 CKS11 CKS10 TMMD11TMMD10 TOLEV1 TOEN1 compare register compare register 01 (CMP01) 11 (CMP11) TOH1/ INTP5/ Decoder Selector Output latch...
Page 158 CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read/written by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n) Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H Symbol...
Page 159: Registers Controlling 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 The following three registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) • Port mode register 1 (PM1) •...
Page 160 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H Symbol <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) Note 1...
Page 161 CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H0 is not guaranteed.
Page 162 CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the Ring-OSC clock, the operation of 8-bit timer H1 is not guaranteed (except when CKS12, CKS11, CKS10 = 1, 0, 1 (f 2.
Page 163: Operation Of 8-Bit Timers H0 And H1
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
Page 164 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-9. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n...
Page 165 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-9. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...
Page 166: Operation As Pwm Output Mode
CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
Page 167 CHAPTER 8 8-BIT TIMERS H0 AND H1 <4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register.
Page 168 CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H ≤...
Page 169 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-11. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
Page 170 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-11. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
Page 171 CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-11. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n...
Page 172: Chapter 9 Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 16 RESET FUNCTION.
Page 173 CHAPTER 9 WATCHDOG TIMER Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Ring-OSC Cannot Be Stopped Ring-OSC Can Be Stopped by Software • Selectable by software (f Note 1 Watchdog timer clock Fixed to f source stopped) •...
Page 174: Configuration Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 9-1. Block Diagram of Watchdog Timer Clock Output 16-bit...
Page 175 CHAPTER 9 WATCHDOG TIMER Figure 9-2. Format of Watchdog Timer Mode Register (WDTM) Address: FF98H After reset: 67H Symbol WDCS4 WDCS3 WDCS2 WDCS1 WDCS0 WDTM Note 1 Note 1 WDCS4 WDCS3 Operation clock selection Ring-OSC clock (f High-speed system clock (f ×...
Page 176 CHAPTER 9 WATCHDOG TIMER (2) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 9AH. Figure 9-3.
Page 177: Operation Of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 9.4 Operation of Watchdog Timer 9.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to Ring-OSC. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
Page 178: Watchdog Timer Operation When "Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte
CHAPTER 9 WATCHDOG TIMER 9.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the high-speed system clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1) of the Ring-OSC clock.
Page 179: Watchdog Timer Operation In Stop Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte)
CHAPTER 9 WATCHDOG TIMER 9.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the high-speed system clock or Ring-OSC clock is being used. (1) When the CPU clock and the watchdog timer operation clock are the high-speed system clock (f ) when the STOP instruction is executed...
Page 180 CHAPTER 9 WATCHDOG TIMER (3) When the CPU clock is the Ring-OSC clock (f ) and the watchdog timer operation clock is the high-speed system clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is stopped until the timing of <1>...
Page 181: Watchdog Timer Operation In Halt Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte)
CHAPTER 9 WATCHDOG TIMER (4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f ) during STOP instruction execution When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, counting is started again using the operation clock before the operation was stopped.
Page 182: Chapter 10 A/D Converter
CHAPTER 10 A/D CONVERTER 10.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following two functions. (1) 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3.
Page 183: Configuration Of A/D Converter
CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter includes the following hardware. Table 10-1. Registers of A/D Converter Used on Software Item Configuration Registers Successive approximation register (SAR) A/D conversion result register (ADCR) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power-fail comparison mode register (PFM) Power-fail comparison threshold register (PFT)
Page 184 CHAPTER 10 A/D CONVERTER (6) A/D conversion result register (ADCR) The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its higher 10 bits (the lower 6 bits are fixed to 0).
Page 185: Registers Used In A/D Converter
CHAPTER 10 A/D CONVERTER 10.3 Registers Used in A/D Converter The A/D converter uses the following five registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • A/D conversion result register (ADCR) • Power-fail comparison mode register (PFM) •...
Page 186 CHAPTER 10 A/D CONVERTER Table 10-2. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only reference voltage generator consumes power) Note Conversion mode (reference voltage generator operation stopped Conversion mode (reference voltage generator operates) Note Data of first conversion cannot be used.
Page 187 CHAPTER 10 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the analog voltage input port to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 10-5.
Page 188 CHAPTER 10 A/D CONVERTER (4) Power-fail comparison mode register (PFM) The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the ADCR register) and the value of the power-fail comparison threshold value register (PFT). PFM can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 189: A/D Converter Operations
CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion using the analog input channel specification register (ADS). µ <2> Set ADCE to 1 and wait for 14 s or longer. <3>...
Page 190 CHAPTER 10 A/D CONVERTER Figure 10-9. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 191: Input Voltage And Conversion Results
CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression. ×...
Page 192: A/D Converter Operation Mode
CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One analog input channel is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. In addition, the following two functions can be selected by setting bit 7 (PFEN) of the power-fail comparison mode register (PFM).
Page 193 CHAPTER 10 A/D CONVERTER (2) Power-fail detection function (when PFEN = 1) By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin specified by the analog input channel specification register (ADS) is started.
Page 194 CHAPTER 10 A/D CONVERTER The setting methods are described below. • When used as A/D conversion operation <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1 and ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
Page 195: How To Read A/D Converter Characteristics Table
CHAPTER 10 A/D CONVERTER 10.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 196 CHAPTER 10 A/D CONVERTER (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0..000 to 0..001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.
Page 197: Cautions For A/D Converter
CHAPTER 10 A/D CONVERTER (8) Conversion time This expresses the time since sampling has been started until digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time...
Page 198 CHAPTER 10 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AV and ANI0 to ANI3 pins. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in Figure 10-19, to reduce noise.
Page 199 CHAPTER 10 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 200 CHAPTER 10 A/D CONVERTER (11) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). A delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required regarding the contents shown in Figure 10-21 and Table 10-3.
Page 201 CHAPTER 10 A/D CONVERTER (12) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-22. Internal Equivalent Circuit of ANIn Pin ANIn Table 10-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 2.7 V 12 kΩ...
Page 202: Chapter 11 Serial Interface Uart0 ( Μ Pd78F0102H And 78F0103H Only)
µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) 11.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 203: Configuration Of Serial Interface Uart0
µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) 11.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 11-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0)
Page 204 Figure 11-1. Block Diagram of Serial Interface UART0 Filter SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial Asynchronous serial INTSR0 Reception control Receive buffer register 0 Baud rate interface operation mode interface reception error (RXB0) generator register 0 (ASIM0) status register 0 (ASIS0) Reception unit Internal bus 8-bit timer/...
Page 205 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).
Page 206: Registers Controlling Serial Interface Uart0
µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) 11.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. • Asynchronous serial interface operation mode register 0 (ASIM0) • Asynchronous serial interface reception error status register 0 (ASIS0) •...
Page 207 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) Figure 11-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 208 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction.
Page 209 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to 1FH.
Page 210 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring- OSC clock, the operation of serial interface UART0 is not guaranteed.
Page 211: Operation Of Serial Interface Uart0
µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) 11.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 11.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.
Page 212: Asynchronous Serial Interface (Uart) Mode
µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) 11.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 213 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 11-6 and 11-7 show the format and waveform example of the normal transmit/receive data. Figure 11-6. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity...
Page 214 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 215 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (c) Transmission The T D0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
Page 216 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the R D0 pin input is detected.
Page 217 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt request (INTSR0) is generated.
Page 218: Dedicated Baud Rate Generator
µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) 11.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception.
Page 219 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (2) Generation of serial clock A serial clock can be generated by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter.
Page 220 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (3) Example of setting baud rate Table 11-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS01, Calculated ERR[%] TPS01, Calculated ERR[%]...
Page 221 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 222 µ CHAPTER 11 SERIAL INTERFACE UART0 ( PD78F0102H AND 78F0103H ONLY) k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. −...
Page 223: Chapter 12 Serial Interface Uart6
CHAPTER 12 SERIAL INTERFACE UART6 12.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 224 CHAPTER 12 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
Page 225 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-2. LIN Reception Operation Wakeup Synchronous Synchronous Indent Data field Data field Checksum signal frame break field field field field Sleep Data Data Data Note 5 reception reception reception reception reception Note 2 13 bits reception Disable Enable...
Page 226 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0 INTP0 input Port mode Port input (PM120) switch control (ISC0) Output latch <ISC0> (P120) 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector...
Page 227: Configuration Of Serial Interface Uart6
CHAPTER 12 SERIAL INTERFACE UART6 12.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 12-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Page 228 Figure 12-4. Block Diagram of Serial Interface UART6 Note TI000, INTP0 Filter INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Baud rate Asynchronous serial interface Receive buffer register 6 interface operation mode interface reception error generator control register 6 (ASICL6) (RXB6)
Page 229 CHAPTER 12 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6).
Page 230: Registers Controlling Serial Interface Uart6
CHAPTER 12 SERIAL INTERFACE UART6 12.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 231 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity.
Page 232 CHAPTER 12 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 233 CHAPTER 12 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 234 CHAPTER 12 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 235 CHAPTER 12 SERIAL INTERFACE UART6 Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring- OSC clock, the operation of serial interface UART6 is not guaranteed.
Page 236 CHAPTER 12 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. RESET input sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 237 CHAPTER 12 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 238 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
Page 239 CHAPTER 12 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input source is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 240: Operation Of Serial Interface Uart6
CHAPTER 12 SERIAL INTERFACE UART6 12.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 12.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 241: Asynchronous Serial Interface (Uart) Mode
CHAPTER 12 SERIAL INTERFACE UART6 12.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 242 CHAPTER 12 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 12-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM13 PM14 UART6 Pin Function Operation TxD6/P13 RxD6/P14 Note Note Note Note × ×...
Page 243 CHAPTER 12 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 12-13 and 12-14 show the format and waveform example of the normal transmit/receive data. Figure 12-13. Format of Normal UART Transmit/Receive Data 1.
Page 244 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
Page 245 CHAPTER 12 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 246 CHAPTER 12 SERIAL INTERFACE UART6 (c) Normal transmission The T D6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 247 CHAPTER 12 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 248 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-16 shows an example of the continuous transmission processing flow. Figure 12-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6. Transmission completion interrupt occurs?
Page 249 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-17 shows the timing of starting continuous transmission, and Figure 12-18 shows the timing of ending continuous transmission. Figure 12-17. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...
Page 250 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-18. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...
Page 251 CHAPTER 12 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 252 CHAPTER 12 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 253 CHAPTER 12 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 254 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-22. Example of Setting Procedure of SBF Transmission (Flowchart) Start Read BRGC6 register and save current set value of BRGC6 register to general- purpose register. Clear TXE6 and RXE6 bits of ASIM6 register to 0 (to disable transmission/ reception).
Page 255 CHAPTER 12 SERIAL INTERFACE UART6 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 12-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
Page 256: Dedicated Baud Rate Generator
CHAPTER 12 SERIAL INTERFACE UART6 12.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 257 CHAPTER 12 SERIAL INTERFACE UART6 Figure 12-25. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6...
Page 258 CHAPTER 12 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
Page 259 CHAPTER 12 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 12-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS60...
Page 260 CHAPTER 12 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 261 CHAPTER 12 SERIAL INTERFACE UART6 Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows. 21k − 2 k + 2 ×...
Page 262 CHAPTER 12 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 263: Chapter 13 Serial Interface Csi10
CHAPTER 13 SERIAL INTERFACE CSI10 13.1 Functions of Serial Interface CSI10 Serial interface CSI10 has the following two modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption.
Page 264 CHAPTER 13 SERIAL INTERFACE CSI10 Figure 13-1. Block Diagram of Serial Interface CSI10 Internal bus Serial I/O shift Transmit buffer Output Note SI10/P11(/RxD0 register 10 (SIO10) register 10 (SOTB10) selector SO10/P12 Output latch PM12 (P12) Transmit data Output latch controller Transmit controller Clock start/stop controller &...
Page 265: Registers Controlling Serial Interface Csi10
CHAPTER 13 SERIAL INTERFACE CSI10 13.3 Registers Controlling Serial Interface CSI10 Serial interface CSI10 is controlled by the following four registers. • Serial operation mode register 10 (CSIM10) • Serial clock selection register 10 (CSIC10) • Port mode register 1 (PM1) •...
Page 266 CHAPTER 13 SERIAL INTERFACE CSI10 (2) Serial clock selection register 10 (CSIC10) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 13-3.
Page 267 CHAPTER 13 SERIAL INTERFACE CSI10 Cautions 1. When the Ring-OSC clock is selected as the clock supplied to the CPU, the clock of the Ring- OSC oscillator is divided and supplied as the serial clock. At this time, the operation of serial interface CSI10 is not guaranteed.
Page 268: Operation Of Serial Interface Csi10
CHAPTER 13 SERIAL INTERFACE CSI10 13.4 Operation of Serial Interface CSI10 Serial interface CSI10 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 13.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In Note Note addition, the P10/SCK10(/T...
Page 269: 3-Wire Serial I/O Mode
CHAPTER 13 SERIAL INTERFACE CSI10 13.4.2 3-wire serial I/O mode The 3-wire serial I/O mode can be used for connecting peripheral ICs and display controllers that have a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines.
Page 270 CHAPTER 13 SERIAL INTERFACE CSI10 The relationship between the register settings and pins is shown below. Table 13-2. Relationship Between Register Settings and Pins CSIE10 PM11 PM12 PM10 CSI10 Pin Function TRMD10 Operation P11/SI10 P12/SO10 P10/SCK10 Note 4 Note 4 (/RxD0 (/TxD0 Note 1...
Page 271 CHAPTER 13 SERIAL INTERFACE CSI10 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10).
Page 272 CHAPTER 13 SERIAL INTERFACE CSI10 Figure 13-5. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 CSOT10 INTCSI10 CSIIF10 SI10 (input AAH)
Page 273 CHAPTER 13 SERIAL INTERFACE CSI10 Figure 13-6. Timing of Clock/Data Phase (a) Type 1; CKP10 = 0, DAP10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 (b) Type 2; CKP10 = 0, DAP10 = 1 SCK10 SI10 capture SO10...
Page 274 CHAPTER 13 SERIAL INTERFACE CSI10 (3) Timing of output to SO10 pin (first bit) When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin. The output operation of the first bit at this time is described below. Figure 13-7.
Page 275 CHAPTER 13 SERIAL INTERFACE CSI10 (4) Output value of SO10 pin (last bit) After communication has been completed, the SO10 pin holds the output value of the last bit. Figure 13-8. Output Value of SO10 Pin (Last Bit) (1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0) SCK10 ( ←...
Page 276 CHAPTER 13 SERIAL INTERFACE CSI10 (5) SO10 output The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is cleared to 0. Table 13-3. SO10 Output Status Note 1 TRMD10 DAP10 DIR10 SO10 Output...
Page 277: Chapter 14 Interrupt Functions
CHAPTER 14 INTERRUPT FUNCTIONS 14.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L). Multiple interrupt servicing of high-priority interrupts can be applied to low priority interrupts.
Page 278 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 279 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP5) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 280: Registers Controlling Interrupt Function
CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Registers Controlling Interrupt Function The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specification flag register (PR0L, PR0H, PR1L) •...
Page 281 CHAPTER 14 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 282 CHAPTER 14 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register MK0, they are set with a 16-bit memory manipulation instruction.
Page 283 CHAPTER 14 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
Page 284 CHAPTER 14 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP5. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 285 CHAPTER 14 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 286: Interrupt Servicing Operations
CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operations 14.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 287 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 288: Software Interrupt Request Acknowledgment
CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 14-9.
Page 289: Multiple Interrupt Servicing
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment.
Page 290 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 291 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 IE = 0...
Page 292: Interrupt Request Hold
CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 293: Chapter 15 Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function Table 15-1. Relationship Between Operation Clocks in Each Operation Status Status High-Speed Ring-OSC Oscillator CPU Clock Prescaler Clock Supplied to System Clock After Peripherals Oscillator Release Note 1 Note 2 MCM0 = 0 MCM0 = 1...
Page 294 CHAPTER 15 STANDBY FUNCTION (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. If the high-speed system clock and Ring-OSC clock oscillator are operating before the HALT mode is set, oscillation of the high-speed system clock and Ring-OSC clock continues.
Page 295: Registers Controlling Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the status register of the high-speed system clock oscillation stabilization time counter.
Page 296 CHAPTER 15 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the oscillation stabilization wait time of the high-speed system clock when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released when the high-speed system clock is selected as the CPU clock.
Page 297: Standby Function Operation
CHAPTER 15 STANDBY FUNCTION 15.2 Standby Function Operation 15.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set when the CPU clock before the setting was the high-speed system clock or Ring-OSC clock. The operating statuses in the HALT mode are shown below.
Page 298 CHAPTER 15 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Page 299 CHAPTER 15 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 15-4.
Page 300: Stop Mode
CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. It can be set when the CPU clock before the setting was the high-speed system clock or Ring-OSC clock. Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.
Page 301 CHAPTER 15 STANDBY FUNCTION (2) STOP mode release Figure 15-5. Operation Timing When STOP Mode Is Released STOP mode release STOP mode High-speed system clock Ring-OSC clock High-speed system clock is selected as HALT status High-speed system clock CPU clock when STOP (oscillation stabilization time set by OSTS) instruction is executed Ring-OSC clock is...
Page 302 CHAPTER 15 STANDBY FUNCTION The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 303 CHAPTER 15 STANDBY FUNCTION (b) Release by RESET input When the RESET signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 15-7. STOP Mode Release by RESET Input (1) When high-speed system clock is used as CPU clock STOP instruction...
Page 304: Chapter 16 Reset Function
CHAPTER 16 RESET FUNCTION The following five operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by clock monitor high-speed system clock oscillation stop detection (4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 305 Figure 16-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF CLMRF LVIRF Watchdog timer reset signal Clear Clear Clear Clock monitor reset signal Reset signal RESET Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit.
Page 306 CHAPTER 16 RESET FUNCTION Figure 16-2. Timing of Reset by RESET Input Ring-OSC clock High-speed system clock Operation stop Normal operation Reset period CPU clock Normal operation (17/f (Reset processing, Ring-OSC clock) (Oscillation stop) RESET Internal reset signal Delay Delay Port pin Hi-Z (except P130)
Page 307 CHAPTER 16 RESET FUNCTION Figure 16-4. Timing of Reset in STOP Mode by RESET Input Ring-OSC clock High-speed system clock STOP instruction execution Operation stop Normal Normal operation Reset period Stop status CPU clock (17/f operation (Reset processing, Ring-OSC clock) (Oscillation stop) (Oscillation stop) RESET...
Page 308 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Statuses After Reset Acknowledgment (1/2) Hardware Status After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
Page 309 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Status After Reset Acknowledgment Note 1 Serial interface UART0 Receive buffer register 0 (RXB0) Transmit shift register 0 (TXS0) Asynchronous serial interface operation mode register 0 (ASIM0) Baud rate generator control register 0 (BRGC0) Serial interface UART6 Receive buffer register 6 (RXB6)
Page 310: Register For Confirming Reset Source
CHAPTER 16 RESET FUNCTION 16.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KB1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Page 311: Chapter 17 Clock Monitor
CHAPTER 17 CLOCK MONITOR 17.1 Functions of Clock Monitor The clock monitor samples the high-speed system clock using the on-chip Ring-OSC, and generates an internal reset signal when the high-speed system clock is stopped. When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set to 1.
Page 312: Register Controlling Clock Monitor
CHAPTER 17 CLOCK MONITOR 17.3 Register Controlling Clock Monitor The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) This register sets the operation mode of the clock monitor. This register can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H.
Page 313: Operation Of Clock Monitor
CHAPTER 17 CLOCK MONITOR 17.4 Operation of Clock Monitor This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows. <Monitor start condition> When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1). <...
Page 314 CHAPTER 17 CLOCK MONITOR Figure 17-3. Timing of Clock Monitor (1/4) (1) When internal reset is executed by oscillation stop of high-speed system clock 4 clocks of Ring-OSC clock High-speed system clock Ring-OSC clock Internal reset signal CLME CLMRF (2) Clock monitor status after RESET input (CLME = 1 is set after RESET input and during high-speed system clock oscillation stabilization time) Clock supply Normal...
Page 315 CHAPTER 17 CLOCK MONITOR Figure 17-3. Timing of Clock Monitor (2/4) (3) Clock monitor status after RESET input (CLME = 1 is set after RESET input and at the end of high-speed system clock oscillation stabilization time) Normal Clock supply operation CPU operation Reset...
Page 316 CHAPTER 17 CLOCK MONITOR Figure 17-3. Timing of Clock Monitor (3/4) (5) Clock monitor status after STOP mode is released (CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode) Clock supply Normal stopped Normal operation operation...
Page 317 CHAPTER 17 CLOCK MONITOR Figure 17-3. Timing of Clock Monitor (4/4) (7) Clock monitor status after Ring-OSC clock oscillation is stopped by software Normal operation (high-speed system clock) CPU operation High-speed system clock Ring-OSC clock Oscillation stopped Note RSTOP CLME Clock monitor status Monitoring Monitoring...
Page 318: Chapter 18 Power-On-Clear Circuit
CHAPTER 18 POWER-ON-CLEAR CIRCUIT 18.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V = 2.1 V ±0.1 V Note ) and detection voltage (V ), and generates internal reset signal when V <...
Page 319: Configuration Of Power-On-Clear Circuit
CHAPTER 18 POWER-ON-CLEAR CIRCUIT 18.2 Configuration of Power-on-Clear Circuit A block diagram of the power-on-clear circuit is shown in Figure 18-1. Figure 18-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Detection voltage source 18.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V ) are compared, and when V...
Page 320: Cautions For Power-On-Clear Circuit
CHAPTER 18 POWER-ON-CLEAR CIRCUIT 18.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 321 CHAPTER 18 POWER-ON-CLEAR CIRCUIT Figure 18-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF register = 1?
Page 322: Chapter 19 Low-Voltage Detector
CHAPTER 19 LOW-VOLTAGE DETECTOR 19.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V < V •...
Page 323: Registers Controlling Low-Voltage Detector
CHAPTER 19 LOW-VOLTAGE DETECTOR 19.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 324 CHAPTER 19 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. RESET input clears LVIS to 00H. Figure 19-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H Symbol...
Page 325: Operation Of Low-Voltage Detector
CHAPTER 19 LOW-VOLTAGE DETECTOR 19.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when <...
Page 326 CHAPTER 19 LOW-VOLTAGE DETECTOR Figure 19-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) Note 1 <1> LVION flag Not cleared Not cleared (set by software) <3>...
Page 327 CHAPTER 19 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS).
Page 328 CHAPTER 19 LOW-VOLTAGE DETECTOR Figure 19-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) Note 1 <1> <7> Cleared by software LVION flag (set by software) <3>...
Page 329: Cautions For Low-Voltage Detector
CHAPTER 19 LOW-VOLTAGE DETECTOR 19.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
Page 330 CHAPTER 19 LOW-VOLTAGE DETECTOR Figure 19-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage ; The Ring-OSC clock is set as the CPU clock when the reset signal is generated Reset Checking cause The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
Page 331 CHAPTER 19 LOW-VOLTAGE DETECTOR Figure 19-6. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset cause WDTRF of RESF register = 1? Reset processing by watchdog timer CLMRF of RESF register = 1? Reset processing by clock monitor LVIRF of RESF register = 1?
Page 332: Chapter 20 Option Byte
CHAPTER 20 OPTION BYTE The 78K0/KB1+ has an area called an option byte at address 0080H of the flash memory. When using the product, be sure to set the following functions by using the option byte. (1) Selection of high-speed system clock oscillation •...
Page 333: Chapter 21 Flash Memory
CHAPTER 21 FLASH MEMORY µ µ PD78F0101H, 78F0102H, and 78F0103H replace the PD780101, 780102, and 780103 of the 78K0/KB1 with flash memory to which a program can be written, erased, and overwritten while mounted on the board. Table 21- 1 lists the differences between the 78K0/KB1+ and the 78K0/KB1. Table 21-1.
Page 334: Internal Memory Size Switching Register
CHAPTER 21 FLASH MEMORY 21.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Caution The initial value of IMS is “setting prohibited (CFH)”.
Page 335: Writing With Flash Programmer
CHAPTER 21 FLASH MEMORY 21.2 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/KB1+ has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system.
Page 336 CHAPTER 21 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 21-2. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode (2.7 to 5.5 V) LVDD FLASH WRITER...
Page 337 CHAPTER 21 FLASH MEMORY Figure 21-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode (2.7 to 5.5 V) LVDD FLASH WRITER /RESET FLMD0 INTERFACE FLMD1 Preliminary User’s Manual U16846EJ1V0UD...
Page 338 CHAPTER 21 FLASH MEMORY Figure 21-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode (2.7 to 5.5 V) LVDD FLASH WRITER /RESET FLMD0 FLMD1 INTERFACE Preliminary User’s Manual U16846EJ1V0UD...
Page 339: Programming Environment
CHAPTER 21 FLASH MEMORY 21.3 Programming Environment The environment required for writing a program to the flash memory of the 78K0/KB1+ is illustrated below. Figure 21-5. Environment for Writing Program to Flash Memory FLMD0 FLMD1 RS-232C Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 78K0/KB1+ Dedicated flash...
Page 340 CHAPTER 21 FLASH MEMORY (2) CSI communication mode supporting handshake Transfer rate: 200 kHz to 2 MHz Figure 21-7. Communication with Dedicated Flash Programmer (CSI10 + HS) FLMD0 FLMD0 FLMD1 FLMD1 Axxxx Bxxxxx /RESET RESET Cxxxxxx STATVE PG-FP4 SI/RxD SO10 78K0/KB1+ Dedicated flash SO/TxD...
Page 341 CHAPTER 21 FLASH MEMORY If Flashpro IV is used as the dedicated flash programmer, Flashpro IV generates the following signal for the 78K0/KB1+. For details, refer to the Flashpro IV Manual. Table 21-4. Pin Connection Flashpro IV 78K0/KB1+ Connection Signal Name Pin Function Pin Name CSI10...
Page 342: Handling Of Pins On Board
CHAPTER 21 FLASH MEMORY 21.5 Handling of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 343: Serial Interface Pins
CHAPTER 21 FLASH MEMORY 21.5.3 Serial interface pins The pins used by each serial interface are listed below. Table 21-5. Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10, SI10, SCK10 CSI10 + HS SO10, SI10, SCK10, HS/P15 UART6 TxD6, RxD6 To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on...
Page 344 CHAPTER 21 FLASH MEMORY (1) Signal collision If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state.
Page 345: Reset Pin
CHAPTER 21 FLASH MEMORY 21.5.4 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator.
Page 346: Programming Method
CHAPTER 21 FLASH MEMORY 21.6 Programming Method 21.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 21-14. Flash Memory Manipulation Procedure Start Flash memory programming FLMD0 pulse supply mode is set Selecting communication mode Manipulate flash memory End? 21.6.2 Flash memory programming mode...
Page 347: Selecting Communication Mode
CHAPTER 21 FLASH MEMORY Table 21-6. Relationship Between FLMD0, FLMD1 Pins and Operation Mode After Reset Release FLMD0 FLMD1 Operation Mode Normal operation mode Flash memory programming mode Setting prohibited 21.6.3 Selecting communication mode In the 78K0/KB1+, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after the dedicated flash memory programming mode is entered.
Page 348: Communication Commands
CHAPTER 21 FLASH MEMORY 21.6.4 Communication commands The 78K0/KB1+ communicates with the dedicated flash programmer by using commands. The signals sent from the flash programmer to the 78K0/KB1+ are called commands, and the commands sent from the 78K0/KB1+ to the dedicated flash programmer are called response commands.
Page 349: Flash Memory Programming By Self-Writing
CHAPTER 21 FLASH MEMORY 21.7 Flash Memory Programming by Self-Writing The 78K0/KB1+ supports a self-programming function that can be used to rewrite the flash memory via a user program, so that the program can be upgraded in the field. The programming mode is selected by bits 0 and 1 (FLSPM0 and FLSPM1) of the flash programming mode control register (FLPMC).
Page 350: Registers Used For Self-Programming Function
CHAPTER 21 FLASH MEMORY 21.7.1 Registers used for self-programming function The following three registers are used for the self-programming function. • Flash-programming mode control register (FLPMC) • Flash protect command register (PFCMD) • Flash status register (PFS) (1) Flash-programming mode control register (FLPMC) This register is used to enable or disable writing or erasing of the flash memory and to set the operation mode during self-programming.
Page 351 CHAPTER 21 FLASH MEMORY Figure 21-18. Format of Flash-Programming Mode Control Register (FLPMC) Note 1 Note 2 Address: FFC4H After reset: 0×H Symbol FLPMC FWEDIS FWEPR FLSPM1 FLSPM0 FWEDIS Control of flash memory writing/erasing Note 3 Writing/erasing enabled Writing/erasing disabled FWEPR Status of FLMD0 pin Low level...
Page 352 CHAPTER 21 FLASH MEMORY (2) Flash protect command register (PFCMD) If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system.
Page 353 CHAPTER 21 FLASH MEMORY The operating conditions of the FPRERR flag are as follows. <Setting conditions> • If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value (A5H) to PFCMD •...
Page 354: Boot Swap Function
CHAPTER 21 FLASH MEMORY 21.8 Boot Swap Function The 78K0/KB1+ has a boot swap function. Even if a momentary power failure occurs for some reason while the boot area is being rewritten by self- programming and the program in the boot area is lost, the boot swap function can execute the program correctly after re-application of power, reset, and start.
Page 355: Memory Map And Boot Area
CHAPTER 21 FLASH MEMORY 21.8.2 Memory map and boot area Figure 21-22 shows the memory map and boot area. The boot program area of the 78K0/KB1+ is in 4 KB units. When boot swap is executed, boot cluster 0 and boot cluster 1 in the figure are exchanged. Figure 21-22.
Page 356 CHAPTER 21 FLASH MEMORY Figure 21-22. Memory Map and Boot Area (2/3) µ PD78F0102H F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H General-purpose registers 32 × 8 bits F E E 0 H F E D F H Internal high-speed RAM...
Page 357 CHAPTER 21 FLASH MEMORY Figure 21-22. Memory Map and Boot Area (3/3) µ PD78F0103H F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H General-purpose registers 32 × 8 bits F E E 0 H F E D F H Internal high-speed RAM...
Page 358: Chapter 22 Instruction Set
CHAPTER 22 INSTRUCTION SET This chapter lists each instruction set of the 78K0/KB1+ in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 22.1 Conventions Used in Operation List 22.1.1 Operand identifiers and specification methods Operands are written in the “Operand”...
Page 359: Description Of Operation Column
CHAPTER 22 INSTRUCTION SET 22.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 360: Operation List
CHAPTER 22 INSTRUCTION SET 22.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 r ← byte − 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte − sfr ← byte sfr, #byte −...
Page 361 CHAPTER 22 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
Page 362 CHAPTER 22 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte × ×...
Page 363 CHAPTER 22 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte − A ← A ∨ r ×...
Page 364 CHAPTER 22 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ← AX − word ×...
Page 365 CHAPTER 22 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit − CY ← CY ∧ A.bit ×...
Page 366 CHAPTER 22 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
Page 367 CHAPTER 22 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 −...
Page 368: Instructions Listed By Addressing Type
CHAPTER 22 INSTRUCTION SET 22.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand [HL + byte] #byte saddr !addr16...
Page 369 CHAPTER 22 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 370 CHAPTER 22 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U16846EJ1V0UD...
Page 371: Chapter 23 Electrical Specifications (Target)
CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) Caution These specifications show target values, which may change after device evaluation. operating voltage range may also change. Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +0.3 −0.3 to V Note + 0.3...
Page 372 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) Crystal/ceramic Oscillator Characteristics = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = AV = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit 4.0 V ≤ V ≤...
Page 373 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V External RC Oscillator Characteristics (T = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit RC oscillation Oscillation frequency 4.0 V ≤...
Page 374 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 DC Characteristics (T = AV = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP.
Page 375 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V , 2.0 V ≤ AV ≤ V Note 1 Note 1 DC Characteristics (T = AV = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply Crystal/ = 16 MHz,...
Page 376 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) AC Characteristics = −40 to +85°C, 2.0 V ≤ V ≤ 5.5 V, 2.0 V ≤ AV ≤ V (1) Basic operation (T = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤...
Page 377 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) vs. V 20.0 16.0 10.0 4.17 Guaranteed operation range 0.238 0.125 2.7 3.3 Supply voltage V Remark The values indicated by the shaded section are only when the Ring-OSC clock is selected. Preliminary User’s Manual U16846EJ1V0UD...
Page 378 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V (2) Serial interface (T = AV = 0 V) (a) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...
Page 379 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) AC Timing Test Points (Excluding X1) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing (MIN.) (MAX.) TI Timing TIL0 TIH0 TI000, TI010 TIL5 TIH5 TI50 Interrupt Request Input Timing INTL INTH INTP0 to INTP5 RESET Input Timing RESET Preliminary User’s Manual U16846EJ1V0UD...
Page 380 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK10 SIKm KSIm SI10 Input data KSOm SO10 Output data Remark m = 1, 2 = −40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤...
Page 381 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C) POC Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage : 0 V → 2.1 V Power supply rise time 0.0015 Note Response delay time 1 When power supply rises, after reaching PTHD detection voltage (MAX.) Note...
Page 382 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) = −40 to +85°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3 LVI4 3.15 3.45 LVI5 2.95 3.25 LVI6 2.85 LVI7 LVI8 2.25 2.35 2.45 LVI9 Note 1 Response time Minimum pulse width...
Page 383 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET) Flash Memory Programming Characteristics = +10 to +65°C, 2.7 V ≤ V ≤ 5.5 V, 2.7 V ≤ AV ≤ V = 0 V) (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit supply current = 10 MHz, V = 5.5 V T.B.D.
Page 384: Chapter 24 Package Drawing
CHAPTER 24 PACKAGE DRAWING 30-PIN PLASTIC SSOP (7.62 mm (300)) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 9.85±0.15 its true position (T.P.) at maximum material condition. 0.45 MAX. 0.65 (T.P.) +0.08 0.24 −0.07 0.1±0.05...
Page 385: Chapter 25 Cautions For Wait
CHAPTER 25 CAUTIONS FOR WAIT 25.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
Page 386: Peripheral Hardware That Generates Wait
CHAPTER 25 CAUTIONS FOR WAIT 25.2 Peripheral Hardware That Generates Wait Table 25-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 25-1. Registers That Generate Wait and Number of CPU Wait Clocks Peripheral Hardware Register Access...
Page 387: Example Of Wait Occurrence
CHAPTER 25 CAUTIONS FOR WAIT 25.3 Example of Wait Occurrence <1> Watchdog timer <On execution of MOV WDTM, A> Number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).) <On execution of MOV WDTM, #byte>...
Page 388: Appendix A Development Tools
Unless otherwise specified, “Windows” means the following OSs. • Windows 3.1 • Windows 95 • Windows 98 • Windows NT Ver 4.0 • Windows 2000 • Windows XP Caution For the development tools of the 78K0/KB1+, contact an NEC Electronics sales representative. Preliminary User’s Manual U16846EJ1V0UD...
Page 389 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/3) (1) When using the in-circuit emulators IE-78K0-NS, IE-78K0-NS-A Software package • Software package Debugging software Language processing software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 390 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/3) (2) When using the in-circuit emulator IE-78K0K1-ET Software package • Software package Debugging software Language processing software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 391 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (3/3) Note 1 (3) When using the in-circuit emulator IECUBE for 78K0/Kx1+ (name pending) Software package • Software package Debugging software Language processing software • Assembler package • Integrated debugger • C compiler package •...
Page 392: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K/0 Series are combined in this package. 78K/0 Series software package µ Part number: S××××SP78K0 Remark ×××× in the part number differs depending on the host machine and OS used. µ...
Page 393: Language Processing Software
APPENDIX A DEVELOPMENT TOOLS A.2 Language Processing Software RA78K0 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller. This assembler is also provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780103H) (sold separately).
Page 394: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 ×××× Host Machine Supply Medium AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD IBM PC/AT compatibles BB13 Windows (English version) AB17...
Page 395: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A Caution The oscillation frequency is up to 10 MHz when the IE-78K0-NS or IE-78K0-NS-A is used. IE-78K0-NS The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K/0 Series product.
Page 396: When Using In-Circuit Emulator Ie-78K0K1-Et
APPENDIX A DEVELOPMENT TOOLS A.5.2 When using in-circuit emulator IE-78K0K1-ET Caution The oscillation frequency is up to 10 MHz when the IE-78K0K1-ET is used. Note IE-78K0K1-ET The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K0/Kx1 or 78K0/Kx1+ product. It corresponds to the integrated debugger (ID78K0-NS).
Page 397: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) SM78K0 This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based System simulator software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine.
Page 398: Appendix B Notes On Target System Design
APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Figure B-1.
Page 399 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Connection Condition of Target System Emulation board (part number pending) Emulation probe NP-30MC Board on end of NP-30MC Guide pin YQ-Guide 13 mm Conversion adapter YSPACK30BK, NSPACK30BK 5 mm 15 mm 20 mm 37 mm 31 mm...
Page 400: Appendix C Register Index
APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Names) A/D conversion result register (ADCR) … 187 A/D converter mode register (ADM) … 185 Analog input channel specification register (ADS) … 187 Asynchronous serial interface control register 6 (ASICL6) … 237 Asynchronous serial interface operation mode register 0 (ASIM0) …...
Page 401 APPENDIX C REGISTER INDEX Interrupt mask flag register 1L (MK1L) … 282 Interrupt request flag register 0H (IF0H) … 281 Interrupt request flag register 0L (IF0L) … 281 Interrupt request flag register 1L (IF1L) … 281 Low-voltage detection level selection register (LVIS) … 324 Low-voltage detection register (LVIM) …...
Page 402 APPENDIX C REGISTER INDEX Serial operation mode register 10 (CSIM10) … 265 Serial I/O shift register 10 (SIO10) … 264 System wait control register (VSWC) … 90 16-bit timer capture/compare register 000 (CR000) … 106 16-bit timer capture/compare register 010 (CR010) … 108 16-bit timer counter 00 (TM00) …...
Page 403: Register Index (In Alphabetical Order With Respect To Register Symbol)
APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ADCR: A/D conversion result register … 187 ADM: A/D converter mode register … 185 ADS: Analog input channel specification register … 187 ASICL6: Asynchronous serial interface control register 6 … 237 ASIF6: Asynchronous serial interface transmission status register 6 …...
Page 404 APPENDIX C REGISTER INDEX MCM: Main clock mode register … 86 MK0H: Interrupt mask flag register 0H … 282 MK0L: Interrupt mask flag register 0L … 282 MK1L: Interrupt mask flag register 1L … 282 MOC: Main OSC control register … 87 OSTC: Oscillation stabilization time counter status register …...
Page 405 APPENDIX C REGISTER INDEX TCL50: Timer clock selection register 50 … 145 TM00: 16-bit timer counter 00 … 106 TM50: 8-bit timer counter 50 … 143 TMC00: 16-bit timer mode control register 00 … 109 TMC50: 8-bit timer mode control register 50 … 146 TMHMD0: 8-bit timer H mode register 0 …...

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Ypd78f0101h Ypd78f0102h Ypd78f0103h

NEC 78K0/KB1+ Preliminary User's Manual

Chapter 1 Outline

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counter 00

Chapter 7 8-Bit Timer/Event Counter 50

Chapter 8 8-Bit Timers H0 and H1

Chapter 9 Watchdog Timer

Chapter 10 A/D Converter

CHAPTER 11 SERIAL INTERFACE UART0 ( Μ PD78F0102H and 78F0103H ONLY)

Chapter 12 Serial Interface Uart6

Chapter 13 Serial Interface Csi10

Chapter 14 Interrupt Functions

Chapter 15 Standby Function

Chapter 16 Reset Function

Chapter 17 Clock Monitor

Chapter 18 Power-On-Clear Circuit

Chapter 19 Low-Voltage Detector

Chapter 20 Option Byte

Chapter 21 Flash Memory

Chapter 22 Instruction Set

Chapter 23 Electrical Specifications (Target)

Chapter 24 Package Drawing

Chapter 25 Cautions for Wait

Appendix A Development Tools

Appendix B Notes on Target System Design

Appendix C Register Index

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Summary of Contents for NEC 78K0/KB1+