Single Channel Ddrcomp; Single Channel Ddrvref And Odtcomp; Single Channel Ddrcvo; Single Channel Ddrcomp Resistive Compensation - Intel Xeon Design Manual

Intel
3.3.7.2

Single Channel DDRCOMP

The MCH uses DDRCOMP_A to calibrate the DDR channel buffers. This is periodically done by
sampling the DDRCOMP pin on the MCH. The Intel E7501 chipset MCH calibrates using a
24.9 Ω ± 1% pull-down to ground. This may be implemented by routing a 15 mils wide trace to a
resistive network as depicted in
any other terminations.
Table 21. DDRCOMP Routing Guidelines
Topology
Nominal Trace Width
Nominal Trace Spacing
Trace Length - MCH to Rtt
Termination Resistor (Rtt)
Termination Voltage
Figure 23. Single Channel DDRCOMP Resistive Compensation
3.3.7.3

Single Channel DDRVREF and ODTCOMP

Follow design guidelines provided in the Intel
Chipset Compatible Platform Design Guide.
3.3.7.4

Single Channel DDRCVO

The MCH uses a compensation signal to adjust buffer characteristics and output voltage swing over
temperature, process, and voltage skew. Calibration is done periodically by sampling the
DDRCVO_A pins on the MCH. Place the voltage divider network (see
of the MCH.
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
Figure
Intel
Parameter
pull-down
15 mils
20 mils
< 1.0"
24.9 Ω ± 1%
Ground
MCH
DDRCOMP_A
®
E7500/E7501 Chipset Compatible Platform
23. Place a decoupling capacitor between the pull-down and
®
E7501 Chipset
MCH
<1"
24.9 Ω ± 1%
®
Xeon™ Processor and Intel
®
E7500/E7501
Figure 24) within one inch
41