Agtl+ I/O Buffer Compensation; Pentium ® M/Celeron ® M Processor Agtl+ I/O Buffer Compensation - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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Figure 28. Intel Pentium
R1
VCCP
4.1.9

AGTL+ I/O Buffer Compensation

The Intel Pentium M/Celeron M processor has four pins, COMP[3:0], and the GMCH has two pins,
HRCOMP[1:0], that require compensation resistors to adjust the AGTL+ I/O buffer characteristics
to specific board and operating environment characteristics. The GMCH requires two special
reference voltage generation circuits to pins HSWNG[1:0] for the same purpose described above.
Refer to the Intel Pentium
M Processor on 90nm Process with 2MB L2 Cache Datasheet and Intel
(GMCH) Datasheet for details on resistive compensation.
4.1.9.1 Pentium
For the Intel Pentium M/Celeron M processor, the COMP[2] and COMP[0] pins (see
each must be pulled-down to ground with 27.4 Ω ± 1% resistors and shall be connected to the Intel
Pentium M/Celeron M processor with a Zo = 27.4 Ω trace that is less than 0.5 inches from the
processor pins. The COMP[3] and COMP[1] pins (see
ground with 54.9 Ω ± 1% resistors and shall be connected to the Intel Pentium M/Celeron M
processor with a Zo = 55 Ω trace that is less than 0.5 inches from the processor pins. COMP[3:0]
traces shall be at least 25 mils (> 50 mils preferred) away from any other toggling signal.
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M/Celeron M Processor GTLREF Motherboard Layout
R2
R2
GTLREF GTLREF GTLREF
Zo =55 Ω Zo =55 Ω Zo = 55 Ω
<0.5" <0.5" <0.5"
Pin E26
Pin E26
PRIMARY SIDE PRIMARY SIDE
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M Processor Datasheet, Intel Celeron
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M/Celeron M Processor AGTL+ I/O Buffer Compensation
January 2007
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6300ESB ICH Embedded Platform Design Guide
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Intel Pentium
Banias
Processor
Figure 30) each must be pulled-down to
Pin AG1
Pin AG1
M
Pin G1 Pin G1 Pin G1
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M Datasheet, Intel Pentium
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855GM/855GME Chipset
Figure
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29)
69