Topology 2B: Cmos Signals Driven By Ich4-M - Dpslp; Figure 13. Routing Illustration For Topology 2A; Figure 14. Routing Illustration For Topology 2B; Table 8. Layout Recommendations For Topology 2A - Intel 852GM Design Manual

Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines
R

Figure 13. Routing Illustration for Topology 2A

Rtt

Table 8. Layout Recommendations for Topology 2A

0.5" – 12.0"
0.5" – 12.0"
4.3.4.5. Topology 2B: CMOS Signals Driven by ICH4-M – DPSLP#
The Topology 2B CMOS DPSLP# signal should adhere to the following routing and layout
recommendations illustrated in Figure 14. As listed in Table 9, the L1 and L2 segments of the DPSLP#
signal topology can be routed as either micro-strip or strip-lines using 55 Ω ± 15% characteristic trace
impedance. Note that the Intel ICH4-M's DPSLP# signal should be routed point-to-point with the daisy
chain topology shown. The routing of DPSLP# at the CPU should fork out to both the ICH4-M and the
GMCH. Segments L1 and L2 from Figure 14 should not T-split from a trace from the Mobile Intel
Pentium 4 Processor–M pin.

Figure 14. Routing Illustration for Topology 2B

Table 9. Layout Recommendations for Topology 2B

®
Intel 852GM Chipset Platform Design Guide
VCCP
L2
L2
L1
0" – 3.0"
0" – 3.0"
GMCH
L2
L1
0.5" – 12.0"
0.5" – 12.0"
CPU
L1
Rtt
300 Ω ± 5%
300 Ω ± 5%
CPU
L2
0.5" – 6.5"
0.5" – 6.5"
ICH4-M
Transmission Line Type
Micro-strip
Strip-line
ICH4-M
L1
Transmission Line Type
Micro-strip
Strip-line
43