Asynchronous Gtl+ Signals Driven By The Processor; Voltage Translation For Ferr; Topology For Asynchronous Gtl+ Signals Driven By The Processor - Intel Xeon Design Manual

Intel
2.3.1

Asynchronous GTL+ Signals Driven by the Processor

Follow the topology shown in
THERMTRIP#. Note that FERR# is the only signal in this group that connects the processors to the
ICH3-S. IERR#, PROCHOT# and THERMTRIP# connect to other motherboard logic (such as the
Baseboard Management Controller) and may need voltage translation logic, depending on the
motherboard receiver logic devices used. Do not route a stub when routing to the processors.
Figure 2. Topology for Asynchronous GTL+ Signals Driven by the Processor
VCC_CPU
Note:
2.3.1.1

Voltage Translation for FERR#

A voltage translator circuit is required for the FERR# signal when VCC_CPU is less than 1.3 V, as
it is for the Low Voltage Intel
given in Figure
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
Figure 2
56Ω ± 5%
Processor
0
3 inches max
Trace Zo - 50Ω
Trace Spacing = 10 ml
®
Xeon™ Processor. The required routing topology for FERR# is
3. Figure 6 shows the voltage translator circuit.
®
E7500/E7501 Chipset Compatible Platform
when routing FERR#, IERR#, PROCHOT# and
1 to 12 inches
VCC_CPU
56Ω ± 5%
®
Intel
ICH3-S
or other
Logic
3 inches max
A9045-01
15