Topology 2B: Asynchronous Gtl+ Signals Driven By Intel; Ich2; Topology 3: Vcciopll, Vcca And Vssa; Figure 39. Routing Illustration For Pwrgood - Intel Pentium 4 Design Manual

R
5.4.1.4

Topology 2B: Asynchronous GTL+ Signals Driven by Intel

This signal (Open Drain; PWRGOOD) should adhere to the following routing and layout
recommendations. Figure 39 illustrates the recommended topology.

Table 18. Layout Recommendations for Miscellaneous Signals (Topology 2B)

Trace Zo
60 Ω

Figure 39. Routing Illustration for PWRGOOD

5.4.1.5

Topology 3: VCCIOPLL, VCCA and VSSA

VCCIOPLL and VCCA are isolated power for internal PLLs. It is critical that they have clean,
noiseless power on their input pins. Keep these signals away from noisy or high frequency signals.
Keep their traces as short as possible. Follow the recommendations in Figure 40 for layout
guidelines. VSSA should not be connected directly to ground on the system board. Further details
can be found in Section 11.4.

Figure 40. Routing Illustration for VCCIOPLL, VCCA and VSSA

VCC_CPU
® ®
Intel Pentium 4 Processor / Intel
Trace Spacing L1
7 mil 1–12"
VCC_CPU
R
PU
L3
4.7 uH
C
A
33 uF
Mother
board
C
IO
33 uF
4.7 uH
®
850 Chipset Family Platform Design Guide
L3 Rpu
3" max
300 Ω ±5%
Processor
L1
VCCA
c2 1 uF
pkg
VSSA
VCCIOPLL
System Bus Routing
®

ICH2

ICH2
Topo2b_pwrgd_Route
PLLs
Processor
Core
VCCIOPLL-VCCA-VSSA_Routing
75