Cmos And Open Drain Signals; Processor Dc Specifications; Gtl+ Signal Group Dc Specifications; Open Drain And Tap Output Signal Group Dc Specifications - Intel BX80562QX6700 - Core 2 Extreme 2.66 GHz Processor Datasheet

2.6.2

CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/
deasserted for at least four BCLKs for the processor to recognize the proper signal
state. See
requirements for entering and leaving the low power states.
2.6.3

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 10.

GTL+ Signal Group DC Specifications

Symbol
V
IL
V
IH
V
OH
I
OL
I
LI
I
LO
R
ON
NOTES:
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
1.
V is defined as the voltage range at a receiving agent that will be interpreted as a logical low
2.
IL
value.
The V
3.
TT
V is defined as the voltage range at a receiving agent that will be interpreted as a logical high
4.
IH
value.
V and V
5.
IH
Leakage to V
6.
Leakage to V
7.
Table 11.

Open Drain and TAP Output Signal Group DC Specifications

Symbol
V
OL
V
OH
I
OL
I
LO
NOTES:
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
1.
2. V is determined by the value of the external pull-up resister to V
OH
Measured at V
3.
For Vin between 0 and V
4.
24
Section 2.6.3 for the DC specifications. See
Parameter
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage
Current
Buffer On Resistance
referred to in these specifications is the instantaneous V
may experience excursions above V
OH
with land held at V
SS
with land held at 300 mV.
TT
Parameter
Output Low Voltage
Output High Voltage
Output Low Current
Output Leakage Current
* 0.2.
TT
.
OH
Section 6.2
Min
-0.10 GTLREF – 0.10
GTLREF + 0.10 V
V – 0.10
TT
N/A
[(R
TT_MIN
N/A
N/A
10
.
TT
.
TT
Min
0
V – 0.05
TT
16
N/A
TT
Electrical Specifications
for additional timing
Max Unit
V
+ 0.10 V
TT
V V
TT
V /
TT_MAX
A
)+(2*R )]
ON_MIN
± 200 µA
± 200 µA
13 Ω
.
TT
Max Unit Notes
0.20 V
V + 0.05 V
TT
50 mA
± 200 µA
.
1
Notes
2, 3
3, 4, 5
3, 5
-
6
7
1
-
2
3
4
Datasheet