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Electrical Specifications
Notes:
1.
Refer to
2.
These signals may be driven simultaneously by multiple agents (Wired-OR).
Table 2-9
non AGTL+ signals including open drain signals.
voltages.
Table 2-8.
AGTL+ Signal Description Table
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,
DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
REQ[4:0]#, RS[2:0]#, RSP#
Table 2-9.
Non AGTL+ Signal Description Table
FORCEPR#
Note:
1.
Signals that have RTT in the package with 50 Ω pullup to V
Table 2-10. Signal Reference Voltages
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPM[5:0]#, BPRI#, BR[1:0]#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#,
HITM#, LOCK#, MCERR#, RESET#, REQ[4:0]#,
RS[2:0]#, RSP#, TRDY#
2.8
CMOS Asynchronous and Open Drain
Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain
signals are required to be asserted/deasserted for at least eight BCLKs in order for the
processor to recognize the proper signal state. See
requirements for entering and leaving the low power states.
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
®
®
Dual-Core Intel
Xeon
Processor 5100 Series Datasheet
Section 5
for signal descriptions.
outlines the signals which include on-die termination (R
AGTL+ signals with R
TT
Signals with R
TT
1
1
, PROCHOT#
GTLREF
TT
Table 2-10
provides signal reference
AGTL+ signals with no R
BPM[5:0]#, RESET#
Signals with no R
A20M#, BCLK[1:0], BSEL[2:0], FERR#/PBE#,
GTLREF_ADD, GTLREF_DATA, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, LL_ID[1:0], MS_ID[1:0], PECI,
PWRGOOD, SKTOCC#, SMI#, STPCLK#, TCK, TDI, TDO,
TESTHI[11:0], THERMTRIP#, TMS, TRDY#, TRST#,
VCC_DIE_SENSE, VCC_DIE_SENSE2, VID[6:1],
VID_SELECT, VSS_DIE_SENSE, VSS_DIE_SENSE2,
VTT_SEL
.
TT
CMOS
A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#,
PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS, TRST#
Chapter 6
for additional timing
).
Table 2-9
outlines
TT
TT
25
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