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®
Intel
855GME Chipset and Intel
When either FERR# or THERMTRIP# is routed to an optional system receiver rather than the
6300ESB and the interface voltage of the optional system receiver does not support a 1.05 V
voltage swing, a voltage translation circuit must be used. When the recommended voltage
translation circuit described in
Figure
22, Rs, shall replace the series dampening resistor R1 in Topology 1B. Thus, R1 is no longer
required in such a topology.
Figure 17. Routing Illustration for Topology 1B
Table 12. Layout Recommendations for Topology 1B
L1
0.5" – 12.0"
0.5" – 12.0"
4.1.5.3
Topology 1C: Open Drain (OD) Signals Driven by the Intel
Pentium M/Celeron M Processor – PROCHOT#
The Topology 1C OD signal PROCHOT#, shall adhere to the following routing and layout
recommendations.
signal of the Intel Pentium M/Celeron M processor. The routing guidelines allow the signal to be
routed as either a micro-strip or strip-line using 55 Ω ± 15 percent characteristic trace impedance.
Figure 18
Intel Pentium M/Celeron M processor's PROCHOT# signal and a system receiver that utilizes a
3.3 V interface voltage (shown as V_IO_RCVR).
Series resistor Rs is a component of the voltage translation logic and serves as a driver isolation
resistor. Rs is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1,
to emphasize the placement of Rs with respect to Q1. The placement of Rs a distance L3 before the
Q1 BJT is a specific implementation of the generalized voltage translator circuit shown in
Figure
22. Rs shall be placed at the beginning of the T-split from the PROCHOT# signal. The
pull-up voltage for termination resistor Rtt is VCCP (1.05 V).
Intel recommends that PROCHOT# be routed using the voltage translation logic shown in
Figure
18. The receiver at the output of the voltage translation circuit may be any system receiver
that may function properly with the PROCHOT# signal given the nature and usage model of this
pin. PROCHOT# is capable of toggling hundreds of times per second to signal a hot temperature
condition.
60
®
6300ESB ICH Embedded Platform Design Guide
Section 4.1.5.7
Figure 17
CPU
L2
0" – 3.0"
0" – 3.0"
0" – 3.0"
0" – 3.0"
Table 13
lists the recommended routing requirements for the PROCHOT#
depicts the recommended implementation for providing voltage translation between the
is used, the driver isolation resistor shown in
depicts the routing illustration for Topology 1B.
®
Intel
6300ESB
(or system receiver)
L2
R
1
L1
L3
R1
56 Ω ± 5%
56 Ω ± 5%
VCCP
Rtt
L3
Transmission
Rtt
Line Type
56 Ω ± 5%
Micro-strip
56 Ω ± 5%
Strip-line
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