Cmos And Open Drain Signals; Processor Dc Specifications; Gtl+ Signal Group Dc Specifications; Open Drain And Tap Output Signal Group Dc Specifications - Intel CORE 2 DUO E4000 - DATASHEET 3-2008 Datasheet
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Also See for CORE 2 DUO E4000 - DATASHEET 3-2008:
- Specification (72 pages) ,
- Design manuallines (148 pages) ,
- Datasheet (122 pages)
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Electrical Specifications
2.7.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-
asserted for at least four BCLKs in order for the processor to recognize the proper
signal state. See
requirements for entering and leaving the low power states.
2.7.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 11.
GTL+ Signal Group DC Specifications
Symbol
V
IL
V
IH
V
OH
I
OL
I
LI
I
LO
R
ON
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
is defined as the voltage range at a receiving agent that will be interpreted as a logical low
IL
value.
3. The V
TT
4. V
is defined as the voltage range at a receiving agent that will be interpreted as a logical high
IH
value.
5. V
and V
IH
6. Leakage to V
7. Leakage to V
.
Table 12.
Open Drain and TAP Output Signal Group DC Specifications
Symbol
V
OL
V
OH
I
OL
I
LO
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
is determined by the value of the external pull-up resister to V
OH
3. Measured at V
4. For Vin between 0 and V
Datasheet
Section 2.7.3
for the DC. See
Parameter
Input Low Voltage
Input High Voltage
GTLREF + 0.10
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage
Current
Buffer On Resistance
referred to in these specifications is the instantaneous V
may experience excursions above V
OH
with land held at V
SS
with land held at 300 mV.
TT
Parameter
Output Low Voltage
Output High Voltage
Output Low Current
Output Leakage Current
* 0.2.
TT
.
OH
Section 6.2
Min
-0.10
GTLREF – 0.10
V
TT
V
– 0.10
TT
V
N/A
[(R
TT_MIN
N/A
N/A
10
.
TT
.
TT
Min
0
V
– 0.05
TT
16
N/A
for additional timing
Max
Unit
Notes
V
+ 0.10
V
V
V
TT
/
TT_MAX
A
)+(2*R
)]
ON_MIN
± 100
µA
± 100
µA
13
Ω
.
TT
Max
Unit
Notes
0.20
V
V
+ 0.05
V
TT
50
mA
± 200
µA
.
TT
1
2, 3
4, 5,
3
5,
3
-
6
7
1
-
2
3
4
27
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