Topology 1A: Open Drain (Od) Signals Driven By The Processor - Ierr; Topology 1B: Open Drain (Od) Signals Driven By The Processor - Ferr# And Thermtrip; Figure 9. Routing Illustration For Topology 1A; Table 10. Layout Recommendations For Topology 1A - Intel 855GM Design Manual

Intel Pentium M/Celeron M Front Side Bus Design Guidelines
4.1.4.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor – IERR#
The Topology 1A OD signal IERR# should adhere to the following routing and layout
recommendations. Table 10 lists the recommended routing requirements for the IERR# signal of the
processor. The routing guidelines allow the signal to be routed as either micro-strip or strip-lines using
55 Ω ± 15% characteristic trace impedance. Series resistor R1 is a dampening resistor for reducing
overshoot/ undershoot reflections on the transmission line. The pull-up voltage for termination resistor
Rtt is VCCP (1.05 V). Due to the dependencies on system design implementation, IERR# can be
implemented in a number of ways to meet design goals. IERR# can be routed as a test point or to any
optional system receiver.

Figure 9. Routing Illustration for Topology 1A

Table 10. Layout Recommendations for Topology 1A

L1
0.5" – 12.0"
0.5" – 12.0"
4.1.4.2. Topology 1B: Open Drain (OD) Signals Driven by the Processor – FERR#
and THERMTRIP#
The Topology 1B OD signals FERR# and THERMTRIP# should adhere to the following routing and
layout recommendations. Table 11 lists the recommended routing requirements for the FERR# and
THERMTRIP# signals of the processor. The routing guidelines allow the signals to be routed as either
micro-strips or strip-lines using 55 Ω ± 15% characteristic trace impedance. Series resistor R1 is a
dampening resistor for reducing overshoot/undershoot reflections on the transmission line. The pull-up
voltage for termination resistor Rtt is VCCP (1.05 V).
Intel recommends that the FERR# signal of the processor be routed to the FERR# signal of the ICH4-M.
THERMTRIP# can be implemented in a number of ways to meet design goals. It can be routed to the
ICH4-M or any optional system receiver. It is recommended that the THERMTRIP# signal of the
processor be routed to the THRMTRIP# signal of the ICH4-M. The ICH4-M's THRMTRIP# signal is a
new signal to the I/O controller hub architecture that allows the ICH4-M to quickly put the whole
system into a S5 state whenever the catastrophic thermal trip point has been reached.
If either FERR# or THERMTRIP# is routed to an optional system receiver rather than the ICH4-M and
the interface voltage of the optional system receiver does not support a 1.05-V voltage swing, then a
voltage translation circuit must be used. If the recommended voltage translation circuit described in
Section 4.1.4.8 is used, the driver isolation resistor shown in Figure 16, Rs, should replace the series
50
CPU
L1
L2 L3
0" – 3.0" 0" – 3.0"
0" – 3.0" 0" – 3.0"
System
Receiver
L2
R1
L3
R1 Rtt
56 Ω ± 5% 56 Ω ± 5%
56 Ω ± 5% 56 Ω ± 5%
®
Intel 855GM/855GME Chipset Platform Design Guide
VCCP
Rtt
Transmission Line Type
Micro-strip
Strip-line
R