Schematic Checklist; Processor Schematic Checklist - Intel Pentium M Processor Design Manual

Schematic Checklist

13.1

Processor Schematic Checklist

Table 95. Processor Schematic Checklist (Sheet 1 of 5)
Checklist Items
1
A[31:3]#
ADSTB[1:0]#
3
D[63:0]#
DINV[3:0]#
DSTBN[3:0]#
DSTBP[3:0]#
REQ[4:0]#
ADS#
BPM[3:0]#
BR0#
DBSY#
DRDY#
LOCK#
BPRI#
DEFER#
RS[2:0]#
8
TRDY#
IERR#
BNR#
HIT#
HITM#
7
RESET#
Design Guide
®
Intel Pentium
Recommendations
® ®
Intel Pentium M Processor System Bus (PSB) Interface Signals
2
9
Connect to processor and the MCH.
4
5
6
Connect to processor and the MCH.
• When IERR# is not used:
– Terminate with 56 Ω ± 5% resistor to
VCCP.
• When IERR# is used:
– Connect to receiver with a 56 Ω ± 5%
series resistor and terminate with 56 Ω ±
5% resistor to VCCP.
Connect to processor and the MCH.
• No ITP debug port present:
– Connect to processor and the MCH.
– On-die termination provides proper
signal quality.
• ITP debug port present:
– Connect to processor and the MCH.
– Pull-up to VCCP through a 54.9 Ω ± 1%
resistor.
®
M Processor and Intel
Refer to
Refer to
Refer to
Refer to
®
E7501 Chipset Platform
Schematic Checklist
Comments
Section 5.1.5.
Section 5.1.6.
Section 5.1.7.1.1.
Section 5.1.6.
• Refer to Section 5.1.4.2.
• For additional information refer to
the ITP700 Debug Port Design
Guide for all schematic, layout
and routing recommendations.
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