Special Consideration Checklist; Clock Generator Checklist - Intel 810A3 Design Manual

Table 8-8. Miscellaneous Checklist for SC242 Processors (Continued)
CPU Pin
PICCLK
SLOTOCC#
TESTHI
THERMDN
THERMDP
VCC_CORE
VID[4:0]
Vtt
NO CONNECTS
Table 8-9. Special Consideration Checklist
Checklist Line Items
GND (VSS)
Table 8-10. Clock Generator Checklist
Checklist Line Items
CPU
SDRAM/DCLK
3V66
PCI
TCLK
OCLK/RCLK
48MHz
APIC
REF
®
Intel 810A3 Chipset Design Guide
I/O
Connect to clock generator / 22-33 Ω series resistor (though OEM needs to
I
simulate based on driver characteristics).
Tie to ground, leave it No Connect, or could be connected to PWRGOOD logic to
O gate system from powering on if no processor is present. If used, 1 KΩ–10 KΩ
pullup resistor to any voltage.
1 KΩ–100 KΩ pullup resistor to VCC_2.5. If a legacy design pulls this up to
I
VCC , use a 1 KΩ–10 KΩ pullup resistor.
CORE
No Connect if not used; otherwise connect to thermal sensor using vendor
O
guidelines.
No Connect if not used; otherwise connect to thermal sensor using vendor
I
guidelines.
I Connect to core voltage regulator. Provide low frequency decoupling.
Connect to on-board VR or VRM. For on-board VR, 10 KΩ pullup resistor to
power-solution compatible voltage required (usually pulled up to input voltage of
O the VR). Some of these solutions have internal pullups. Optional override
(jumpers, ASIC, etc.) could be used. May also connect to system monitoring
device.
I Connect to 1.5V regulator. Provide high and low frequency decoupling.
The following pins must be left as no-connects: A16, A47, A88, A113, A116,
N/A
B12, B20, B76, B112.
Connect AJ3, AL1, and AN3 to ground (Vss). These pins must be grounded.
Series resistor 33 Ω ± 5%.
Series resistor 22 Ω ± 5%.
DCLK cap: 22 pF ± 2%.
Series resistor 22 Ω ± 5%.
cap: 18pF ± 2%.
Series resistor 33 Ω ± 5%.
Series resistor 22 Ω ± 5%.
Series resistor 33 Ω ± 5%.
Series resistor 33 Ω ± 5%.
Series resistor 33 Ω ± 5%.
Series resistor 10 Ω ± 5%.
Design Checklist
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