Clocking; General Clocking Considerations; Host Bus Clock Connections - Intel Pentium III Processor 512K Design Manual

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LV Intel Pentium III Processor 512K Dual Processor Platform
4.0

Clocking

4.1

General Clocking Considerations

The host bus clock signals are critical signals in a platform design. The signal integrity and timing
of these signals should be carefully evaluated and simulated.
In general, the following layout recommendations should be followed for the host bus clocks:
•
It is recommended that system bus clocks be routed on the signal layer next to the ground layer
(referenced to ground).
•
It is strongly recommended that system bus clocks do not traverse multiple signal layers.
•
System clock routing over power plane splits should be minimized.
•
If necessary, grounded guard band traces can be routed next to clock traces to reduce crosstalk
to other signals.
Figure 11 shows the host bus clocking connections that must be made in a LV Intel Pentium
processor 512K system. Detailed information regarding the routing, layout, and termination of the
processor and chipset connections can be found in "Single Ended Host Bus Clocking Routing" on
page 25. The debug port routing has special requirements and are provided in "Debug Port Host
Clock Connection" on page 29.
Figure 11. Host Bus Clock Connections
The clocking requirements and timing information for the LV Intel Pentium
be found in the Low Voltage Intel
information about the timing and clocking requirements of the chipset component, please contact
your chipset vendor for the appropriate documentation.
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Clock Driver
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Pentium
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Processor 512K Datasheet. For additional
III
III
Processor 0
Processor 1
Chipset
PLL
processor 512K can
III
Design Guide