Clk100 Clock Group (Src Clock) Topology; 100 Mhz Src/Src# Clock Routing Guidelines For Pci Express Slot/Component - Intel EP80579 Manual

Platform System Clock—Intel
8.2.2.4 Source Clock to PCI Express* Components or Connectors
Figure 56.

CLK100 Clock Group (SRC Clock) Topology

C lock D river
C K410, D B800
Table 20.

100 MHz SRC/SRC# Clock Routing Guidelines for PCI Express Slot/Component

Trace Width – W
SRC to SRC# spacing – S
SRC to Signal Spacing – S1
(includes spacing between SRC pairs)
Baseboard Impedance – Differential
Clock Routing Length
(L1, L1'): Clock Driver to Rs
Clock Routing Length
(L2, L2'): Rs to Rs-Rt Node
Clock Routing Length
(L3, L3'): Rs-Rt Node to Rt
Routing Length
(L4, L4'): Any Clock driver
(CK410/DB800) to component
Routing Length
(L4,L4'): Any Clock Driver (CK410/DB800) to
PCI Express connector
CLKN – CLKP Length Matching
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
LT = L1 + L2 + L4
R s
L1
L1'
R s
Parameter
1
1
L2 L4
L2' L4'
L3
L3'
R t R t
Routing Guidelines
microstrip: 4.5 mils
stripline: 4.75 mils
10 mils
20 mils
100 Ω ±10%
0.5 in max
0.1 in max
0.1 in max
Min: 3 in
Max: 20 in
Min: 3 in
Max: 16 in
within 5 mils
PCI Express*
Slot/C om ponent
Figure Notes
Figure 57
1
Figure 57 2,3
Figure 57
2,3
Figure 56
4
Figure 56
4
Figure 56
4
Figure 56
5
Figure 56
5
May 2010
98