Clock Group Topologies And Routing Constraints; Figure 106. Clock Distribution Diagram - Intel 852GM Design Manual

Platform Clock Routing Guidelines
Figure 106 below depicts the system clock subsystem including the clock generator, major platform
components, all the related clock interconnects.

Figure 106. Clock Distribution Diagram

11.2.

Clock Group Topologies and Routing Constraints

The topology diagrams and routing constraint tables provided on the following pages define the
recommended topology and routing rules for each of the platform level clocks. These topologies and
rules have been simulated and verified to produce the required waveform integrity and timing
characteristics for reliable platform operation.
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Intel 852GM Chipset Platform Design Guide
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