Contention Between Tcor Write And Input Capture; Figure 9.23 Contention Between Tcor Write And Input Capture - Hitachi H8/3062 Hardware Manual

9.7.6

Contention between TCOR Write and Input Capture

If an input capture signal occurs in the T state of a TCOR write cycle, input capture takes priority
3
and the write to TCOR is not performed. Figure 9.23 shows the timing in this case.
TCOR write cycle
T T T
1 2 3
φ
Address bus TCOR address
Internal write signal
Input capture signal
8TCNT M
TCOR X M

Figure 9.23 Contention between TCOR Write and Input Capture

318