Registers Of External Interrupt/Nmi Controller - Fujitsu MB91260B Series Hardware Manual

CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.2

Registers of External Interrupt/NMI Controller

This section explains the configuration and functions of registers used by external
interrupt/NMI controller.
■ Interrupt Enable Register (ENIR (ENIR0, ENIR1): ENable Interrupt Request Register)
ENIR0 Address: 00000041
ENIR1 Address: 000000B9
ENIR register controls mask of the external interrupt request output. Output for an interrupt request is
enabled based on the bit in this register to which "1" has been written (INT0 enable is controlled by EN0),
and the interrupt request is output to the interrupt controller. The pin corresponding to the bit to which "0"
is written holds the interrupt source but does not generate a request to the interrupt controller.
Please make sure to write "0" to bit7 to bit2 of ENIR1 register.
No enable bit exists for NMI.
■ External Interrupt Source Register (EIRR (EIRR0, EIRR1): External Interrupt Request
Register)
EIRR0 Address: 00000040
EIRR1 Address: 000000B8
EIRR register is a register that shows a corresponding external interrupt request exists when reading, and
that clears a content of the flip-flop showing this request when writing.
If the read value of this EIRR register is "1", there is an external interrupt request at the pin corresponding
to this bit. Write "0" to this register to clear the request flip-flop of the corresponding bit.
Writing "1" to this register is invalid.
"1" is read in a read operation of the read-modify-write.
The flag for NMI cannot be accessed by a user.
132
Bit No. →
7 6
EN7 EN6 EN5
H
– –
H
Bit No. →
7 6
ER7 ER6 ER5
H
– –
H
5 4 3 2
EN4 EN3 EN2
– – – –
5 4 3 2
ER4 ER3 ER2
– – – –
1 0 Initial value
00000000 [R/W]
EN1 EN0
B
- - - - - - 0 0 [R/W]
EN9 EN8
B
1 0 Initial value
00000000
ER1 ER0
B
- - - - - - 0 0 [R/W]
ER9 ER8
B
[R/W]