R&S AFQ100A Operating Manual page 372

R&S AFQ100A
Transmission Specs
data
clock
skew
rise time
Digital Resolution
The user can adjust digital resolution to 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16 bits.
Marker
Independent of the selected digital resolution the user can make the instrument replace several lines of
the output stream by marker signals (see chapter 4, section
Clock Generation
The output signal at port 2 can be generated using either internal or external clock. However, the user
should observe the following aspects:
4. Instrument's output clock and signal ("Forward Clock") are in phase. Signal and clock propagation
delay are equal. The input registers of the receiver circuitry should be configured accordingly.
5. The instrument generates its internal clock by a phase locked loop within digital circuitry. This clock
signal is therefore not appropriate for driving a sophisticated DAC. The same problem arises from
external clocks which are output again at the CLOCK OUT connector. Jitter and noise level of a re-
output clock are worse compared with a dedicated clock of the DAC.
6. An dedicated clock generated by a synthesizer is therefore recommended for the DAC. The data of
the instrument along with its clock signal should be taken over and then be both re synchronized to
the clock signal of the synchronizer and then forwarded to the DAC.
Filter
In parallel mode, the data is not resampled. Time and frequency shifts as well as equalizer features are
not accessible.
1401.3084.32
LVDS, > +/- 200mV at 100Z
LVDS, > +/- 200mV at 100Z
200 ps
400 ps
8.15
Specifications of Digital Interfaces
"Marker Dialog").
E-3