R&S AFQ100A Operating Manual page 371

R&S AFQ100A
Port 2
The memory data are output in two words with a width (length) of 16 bits each. Every word will be
passed over along with a clock signal.
Connector:
The pins are assigned as follows:
Signals for I
LVDS "p"
Pin
Bit 0 (LSB) 1
Bit 1 2
Bit 2 3
Bit 3 4
Bit 4 5
Bit 5 6
Bit 6 7
Bit 7 8
Bit 8 10
Bit 9 11
Bit 10 12
Bit 11 13
Bit 12 14
Bit 13 15
Bit 14 16
Bit 15 (MSB) 17
Clock 9
LVDS "p" und LVDS "n" are a pair of wires (lines). The signals have to be transmitted at a differential
impedance of 100 Z and terminated appropriately to avoid signal reflections.
Note:
Because of large clock rates and high slew rates a proper cabling is necessary: Avoid impedance
discontinuities and branch lines. The differential line should be terminated properly (100 ) and the
resistor must be as close as possible to the line end.
Clock and data are in phase, this means, the rising clock slopes (edge) coincide with the transitions
between two consecutive symbols. Furthermore, the clock can be inverted, hence the falling clock slope
coincides with the transitions between two consecutive symbols (see chapter 4, section
Output").
1401.3084.32
AFQ-B18 - Port 2: PARALLEL DATA
LVDS "n"
Pin
35 Bit 0 (LSB)
36 Bit 1
37 Bit 2
38 Bit 3
39 Bit 4
40 Bit 5
41 Bit 6
42 Bit 7
44 Bit 8
45 Bit 9
46 Bit 10
47 Bit 11
48 Bit 12
49 Bit 13
50 Bit 14
51 Bit 15 (MSB)
43 Clock
Specifications of Digital Interfaces
Signals for Q
LVDS "p" LVDS "n"
Pin Pin
18
19
20
21
22
23
24
25
27
28
29
30
31
32
33
34
26
8.14
52
53
54
55
56
57
58
59
61
62
63
64
65
66
67
68
60
"Slope - Digital
E-3