R&S AFQ100A Operating Manual page 370

R&S AFQ100A
Mapping of I and Q to Muxed Data Stream
Data Bit
11
10
9
8
7
6
5
4
3
2
1
0
As the bits are being collected serially, consecutive groups of six are transmitted on line 1, line 2, line 3
etc.
To get rid of DC components, a DC balance bit is added after the 6th bit, so that seven bits are
transmitted per sample.
The associated clock line transmits 100 MHz (100 Mbits/s) whereby the positive clock slope denotes a
new multiplex word.
National Semiconductor's 48-Bit Channel Link Deserializer DS90CR484 can receive this data stream,
see http://www.national.com/pf/DS/DS90CR484.html.
Apart from the multiplexed data stream the instrument transmits the following data:
SYNC_IN: The desired memory clock rate may be set here.
I2CD, I2CC: The interface transmits supplemented signal data, e.g. signal name, word width
(length), clock rate, usage of IF, etc. See TVR290 for details.
Digital Resolution
The user may set digital resolution to 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16 bits.
Marker
The marker is inserted at the mentioned position into the output stream.
Clock Generation
The output signal at Port 1 will be generated at a base clock rate or 100 MHz. Since the data stream is
multiplexed 7 to 1, this corresponds to a data rate of 700 Mbit/s.
The memory clock may run at a rate selected by the user, the rate must not exceed 100 MHz, of
course.
Filters
In mode a) all features of the instrument can be used, e.g. time and frequency shifts
correction filters in the impairments and equalizer block.
1401.3084.32
Content
I-Data Bit 3
I-Data Bit 2
I-Data Bit 1
I-Data Bit 0
reserved
reserved
reserved
reserved
reserved
Marker 1
ENABLE
VALID
8.13
Specifications of Digital Interfaces
Line
f / t
or the
E-3