R&S AFQ100A Operating Manual page 368

R&S AFQ100A
Port 1
Port 1 drives instrument equipped with a digital I/Q input, providing two modes:
c) The interface runs at 100 MHz clock rate, the data are output from sample memory at an
adjustable clock rate or at an external clock rate and are resampled to 100 MHz. Time and
frequency shifts as well as equalizer features are possible. The user may switch on an IF, i.e. a
frequency offset which will frequency shift the radio signal immediately.
d) The interface runs at 100 MHz clock rate, the data are output from sample memory at an
internal adjustable clock rate or an external clock rate and inserted in the data stream. Valid data
words are labeled as "Enable". The instrument does not resample the signal, this means, the clock
rate is not changed. Time and frequency shifts as well as equalizer features are not accessible.
e)
Connector:
The pins are assigned as follows:
Signals for I and Q
LVDS "p"
Pin
OUT 0 3
OUT 1 4
OUT 2 5
OUT 3 9
OUT 4 10
OUT 5 11
OUT 6 12
OUT 7 13
Clock 6
LVDS "p" und LVDS "n" are a pair of lines. The signals have to be transmitted at a differential
impedance of 100 Ohm and terminated appropriately to avoid signal reflections. The multiplex factor is
7:1, hence a clock rate of 100MHz corresponds to a data rate of 700 Mbit/s.
Serializing and Mapping
I/Q data are transmitted using National Semiconductor's LVDS Channellink technique. Data bits of I and
Q, markers and additional controller cables are mapped to 48 data bits. The option R&S AFQ-B18
generates serial data streams from the 48 bits which are specified below:
1401.3084.32
R&S AFQ-B18 - Port 1: MUXED DATA
LVDS "n"
Pin
15 SYNC In
16 I2C Clock
17 I2C Data
21
22 GND
23 GND
24 GND
25 +5V-Out
18
Specifications of Digital Interfaces
Control Signals
LVDS "p" LVDS "n"
Pin Pin
1 14
7 (3V3-Logic)
20 (3V3-Logic)
2
19
26
8
8.11 E-3