R&S AFQ100A Operating Manual page 29

R&S AFQ100A
4 BERT
Four BERT inputs
Note:
CLOCK
DATA
RESTART
DATA ENABL
1401.3078.62
The BERT connectors either receive clock and data
signals for measuring a bit error rate
or,
they receive control signals for segment hopping
(FHOP) while generating multi segment waveforms.
The sequence for segment hopping can be fed in
parallel or serial.
The FHOP mode disables the BERT functionality and
vice versa. The FHOP mode requires the hardware
revisions: Baseboard 3 Rev. 5.00 and SFB > Rev.
01.05.05.
Clock input from a DUT.
Clock input in mode FHOP serial.
Bit 3 (MSB) input in mode FHOP parallel.
Demodulated data from DUT.
Data input in mode FHOP serial.
Bit 2 input in mode FHOP parallel.
This signal repeats BER measurements with short
signals.
The signal is not used in mode FHOP serial.
Bit 1 input in mode FHOP parallel.
This signal labels the payload of the data, hence
header or guard signals do not contribute to the
BER.
Strobe input in mode FHOP serial to mark the end
of a data sequence( LSB).
Bit 0 (LSB) input in mode FHOP parallel.
Legend for Rear Panel View
1.9
See data sheet and
chapter 4, section
"Trigger Dialog"
E-3