Samsung S5PC100 User Manual page 1508

HDMI
3.14 PIXEL LIMIT VALUE REGISTERS (HDMI_CMAX, R/W, ADDRESS = 0XF030_0068)
HDMI_CMAX
HDMI_CMAX
3.15 PIXEL LIMIT VALUE REGISTERS (HDMI_CMIN, R/W, ADDRESS = 0XF030_006C)
HDMI_CMIN
HDMI_CMIN
3.16 PACKET TRANSMISSION START MARGIN DURING VBI
(VBI_ST_MG, R/W, ADDRESS = 0XF030_0080)
VBI_ST_MG
VBI_ST_MG
9.10-26
Bits
These registers are used according to PX_LMT_CTRL bits in
HDMI_CON_1 register.
For Cb and Cr values,
if (input_color_value > HDMI_CMAX x 16)
output_color_value = HDMI_CMAX x 16
else if (input_color_value < HDMI_CMIN x 16)
[7:0]
output_color_value = HDMI_CMIN x 16
else output_color_value = input_color_value
NOTE: Value 16 at each line is to compensate the difference of bit
width between the input pixels and register value.
Bits
These registers are used according to PX_LMT_CTRL bits in
HDMI_CON_1 register.
For Cb and Cr values,
if (input_color_value > HDMI_CMAX x 16)
output_color_value = HDMI_CMAX x 16
else if (input_color_value < HDMI_CMIN x 16)
[7:0]
output_color_value = HDMI_CMIN x 16
else output_color_value = input_color_value
NOTE: Value 16 at each line is to compensate the difference of bit
width between the input pixels and register value.
Bits
The number of cycles for preventing transmission of any
packet data from the start of the video line during VBI period.
7:0
NOTE: Strongly recommend that do NOT modify this field
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Description
Reset Value
0xF0
Reset Value
0x10
Reset Value
0x3C