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Intel Core i7 Desktop Series Manuals
Manuals and User Guides for Intel Core i7 Desktop Series. We have
3
Intel Core i7 Desktop Series manuals available for free PDF download: Datasheet
INTEL Core i7 Desktop Series Datasheet (290 pages)
Brand:
INTEL
| Category:
Computer Hardware
| Size: 4.43 MB
Table of Contents
Datasheet, Volume
2
Table of Contents
3
Revision History
10
1 Introduction
11
2 Processor Configuration Registers
13
Register Terminology
13
Register Attributes and Terminology
13
PCI Devices and Functions on Processor
14
Register Attribute Modifiers
14
System Address Map
15
System Address Range Example
17
Legacy Address Range
18
DOS Range (0H-9_Ffffh)
18
DOS Legacy Address Range
18
Legacy Video Area (A_0000H-B_Ffffh)
19
PAM (C_0000H-F_Ffffh)
20
Main Memory Address Range (1 MB - TOLUD)
20
Main Memory Address Range
20
ISA Hole (15 MB-16 MB)
21
Tseg
21
Protected Memory Range (PMR) - (Programmable)
21
DRAM Protected Range (DPR)
22
Pre-Allocated Memory
22
GFX Stolen Spaces
23
Me Uma
23
PCI Memory Address Range (TOLUD - 4 GB)
23
PCI Memory Address Range
24
APIC Configuration Space (Fec0_0000H-Fecf_Ffffh)
25
HSEG (Feda_0000H-Fedb_Ffffh)
25
MSI Interrupt Memory Space (Fee0_0000H-Feef_Ffffh)
25
High BIOS Area
25
Main Memory Address Space (4 GB to TOUUD)
26
Indirect Accesses to MCHBAR Registers
27
Memory Re-Claim Background
27
Hardware Remap Algorithm
28
Memory Remapping
28
Programming Model
28
Case 1: Less than 4 GB of Physical Memory (no Remap)
29
Case 2: Greater than 4 GB of Physical Memory
30
PCI Express* Configuration Address Space
32
PCI Express* Graphics Attach (PEG)
33
Graphics Memory Address Ranges
34
IOBAR Mapped Access to Device 2 MMIO Space
34
Trusted Graphics Ranges
34
ME Stolen Memory Accesses
35
SMM and VGA Access through GTT TLB
35
System Management Mode (SMM)
35
SMM Regions
35
I/O Address Space
36
PCI Express* I/O Address Mapping
36
Decode Rules and Cross-Bridge Address Mapping
37
DMI Interface Decode Rules
37
MCTP and KVM Flows
37
Example: DMI Upstream VC0 Memory Map
39
PCI Express* Interface Decode Rules
40
Legacy VGA and I/O Range Decode Rules
41
PEG Upstream VC0 Memory Map
41
IGD Frame Buffer Accesses
42
IGD VGA I/O Mapping
42
VGA and MDA I/O Transaction Mapping
43
Processor Register Introduction
45
I/O Mapped Registers
46
PCI Device 0 Function 0 Configuration Space
46
PCI Device 0, Function 0 Register Address Map
46
VID-Vendor Identification Register
48
DID-Device Identification Register
48
PCICMD-PCI Command Register
49
PCISTS-PCI Status Register
50
RID-Revision Identification Register
52
CC-Class Code Register
53
HDR-Header Type Register
53
SVID-Subsystem Vendor Identification Register
54
SID-Subsystem Identification Register
54
PXPEPBAR-PCI Express Egress Port Base Address Register
55
MCHBAR-Host Memory Mapped Register Range Base Register
56
GGC-GMCH Graphics Control Register Register
57
DEVEN-Device Enable Register
59
PCIEXBAR-PCI Express Register Range Base Address Register
60
DMIBAR-Root Complex Register Range Base Address Register
62
PAM0-Programmable Attribute Map 0 Register
63
PAM1-Programmable Attribute Map 1 Register
64
PAM2-Programmable Attribute Map 2 Register
65
PAM3-Programmable Attribute Map 3 Register
66
PAM4-Programmable Attribute Map 4 Register
67
PAM5-Programmable Attribute Map 5 Register
68
PAM6-Programmable Attribute Map 6 Register
69
LAC-Legacy Access Control Register
70
REMAPBASE-Remap Base Address Register
74
REMAPLIMIT-Remap Limit Address Register
74
TOM-Top of Memory Register
75
TOUUD-Top of Upper Usable DRAM Register
76
BDSM-Base Data of Stolen Memory Register
77
BGSM-Base of GTT Stolen Memory Register
77
G Memory Base Register
78
TOLUD-Top of Low Usable DRAM Register
78
SKPD-Scratchpad Data Register
79
CAPID0_A-Capabilities a Register
80
PCI Device 1 Function 0-2 Configuration Space
82
PCI Device 1, Function 0-2 Configuration Register Address Map
82
VID1-Vendor Identification Register
84
DID1-Device Identification Register
84
PCICMD1-PCI Command Register
85
PCISTS1-PCI Status Register
87
RID1-Revision Identification Register
89
CC1-Class Code Register
89
CL1-Cache Line Size Register
90
HDR1-Header Type Register
90
PBUSN1-Primary Bus Number Register
90
SBUSN1-Secondary Bus Number Register
91
SUBUSN1-Subordinate Bus Number Register
91
IOBASE1-I/O Base Address Register
92
IOLIMIT1-I/O Limit Address Register
92
SSTS1-Secondary Status Register
93
MBASE1-Memory Base Address Register
94
MLIMIT1-Memory Limit Address Register
95
PMBASE1-Prefetchable Memory Base Address Register
96
PMLIMIT1-Prefetchable Memory Limit Address Register
97
PMBASEU1-Prefetchable Memory Base Address Upper Register
98
PMLIMITU1-Prefetchable Memory Limit Address Upper Register
98
CAPPTR1-Capabilities Pointer Register
99
INTRLINE1-Interrupt Line Register
99
INTRPIN1-Interrupt Pin Register
100
BCTRL1-Bridge Control Register
100
PM_CAPID1-Power Management Capabilities Register
102
PM_CS1-Power Management Control/Status Register
103
SS_CAPID-Subsystem ID and Vendor ID Capabilities Register
104
SS-Subsystem ID and Subsystem Vendor ID Register
105
MSI_CAPID-Message Signaled Interrupts Capability ID Register
105
MC-Message Control Register
106
MA-Message Address Register
107
MD-Message Data Register
107
PEG_CAPL-PCI Express-G Capability List Register
107
DCAP-Device Capabilities Register
108
PEG_CAP-PCI Express-G Capabilities Register
108
DCTL-Device Control Register
109
DSTS-Device Status Register
110
LCTL-Link Control Register
111
LSTS-Link Status Register
113
SLOTCAP-Slot Capabilities Register
114
SLOTCTL-Slot Control Register
116
SLOTSTS-Slot Status Register
118
LCTL2-Link Control 2 Register
120
RCTL-Root Control Register
120
PCI Device 1 Function 0-2 Extended Configuration
123
PVCCAP1-Port VC Capability Register 1
123
PCI Device 1 Function 0-2 Extended Configuration Register Address Map
123
PVCCAP2-Port VC Capability Register 2
124
PVCCTL-Port VC Control Register
124
VC0RCAP-VC0 Resource Capability Register
125
VC0RCTL-VC0 Resource Control Register
126
VC0RSTS-VC0 Resource Status Register
127
PEG_TC-PCI Express Completion Time-Out Register
127
PCI Device 2 Configuration Space
128
PCI Device 2 Configuration Register Address Map
128
VID2-Vendor Identification Register
129
DID2-Device Identification Register
129
PCICMD2-PCI Command Register
130
PCISTS2-PCI Status Register
131
RID2-Revision Identification Register
132
CC-Class Code Register
132
CLS-Cache Line Size Register
133
MTXT2-Master Latency Timer Register
133
HDR2-Header Type Register
133
GTTMMADR-Graphics Translation Table, Memory Mapped Range Address Register
134
GMADR-Graphics Memory Range Address Register
135
IOBAR-I/O Base Address Register
136
SVID2-Subsystem Vendor Identification Register
136
SID2-Subsystem Identification Register
137
ROMADR-Video BIOS ROM Base Address Register
137
INTRPIN-Interrupt Pin Register
137
MINGNT-Minimum Grant Register
138
MAXLAT-Maximum Latency Register
138
MSAC-Multi Size Aperture Control Register
139
Device 2 IO
140
DATA-MMIO Data Register
140
INDEX-MMIO Address Register
140
PCI Device 6
141
PCI Device 6 Register Address Map
141
DID6-Device Identification Register
143
VID6-Vendor Identification Register
143
PCICMD6-PCI Command Register
144
PCISTS6-PCI Status Register
146
CC6-Class Code Register
148
RID6-Revision Identification Register
148
CL6-Cache Line Size Register
149
HDR6-Header Type Register
149
PBUSN6-Primary Bus Number Register
149
SBUSN6-Secondary Bus Number Register
150
SUBUSN6-Subordinate Bus Number Register
150
IOBASE6-I/O Base Address Register
151
IOLIMIT6-I/O Limit Address Register
151
SSTS6-Secondary Status Register
152
MBASE6-Memory Base Address Register
153
MLIMIT6-Memory Limit Address Register
154
PMBASE6-Prefetchable Memory Base Address Register
155
PMLIMIT6-Prefetchable Memory Limit Address Register
156
PMBASEU6-Prefetchable Memory Base Address Upper Register
157
PMLIMITU6-Prefetchable Memory Limit Address Upper Register
158
CAPPTR6-Capabilities Pointer Register
158
INTRLINE6-Interrupt Line Register
159
INTRPIN6-Interrupt Pin Register
159
BCTRL6-Bridge Control Register
160
PM_CAPID6-Power Management Capabilities Register
162
PM_CS6-Power Management Control/Status Register
163
SS_CAPID-Subsystem ID and Vendor ID Capabilities Register
164
SS-Subsystem ID and Subsystem Vendor ID Register
165
MSI_CAPID-Message Signaled Interrupts Capability ID Register
165
MC-Message Control Register
166
MA-Message Address Register
167
MD-Message Data Register
167
PEG_CAPL-PCI Express-G Capability List Register
167
PEG_CAP-PCI Express-G Capabilities Register
168
DCAP-Device Capabilities Register
168
DCTL-Device Control Register
169
DSTS-Device Status Register
170
LCTL-Link Control Register
171
LSTS-Link Status Register
173
SLOTCAP-Slot Capabilities Register
174
SLOTCTL-Slot Control Register
176
SLOTSTS-Slot Status Register
178
RCTL-Root Control Register
179
PCI Device 6 Extended Configuration
180
PVCCAP1-Port VC Capability Register 1
180
PCI Device 6 Extended Configuration Register Address Map
180
PVCCAP2-Port VC Capability Register 2
181
PVCCTL-Port VC Control Register
181
VC0RCAP-VC0 Resource Capability Register
182
VC0RCTL-VC0 Resource Control Register
183
VC0RSTS-VC0 Resource Status Register
184
Dmibar
185
DMIVCECH-DMI Virtual Channel Enhanced Capability Register
186
DMIPVCCAP1-DMI Port VC Capability Register 1
187
DMIPVCCAP2-DMI Port VC Capability Register 2
187
DMIPVCCTL-DMI Port VC Control Register
188
DMIVC0RCAP-DMI VC0 Resource Capability Register
188
DMIVC0RCTL-DMI VC0 Resource Control Register
189
DMIVC0RSTS-DMI VC0 Resource Status Register
190
DMIVC1RCAP-DMI VC1 Resource Capability Register
190
DMIVC1RCTL-DMI VC1 Resource Control Register
191
DMIVC1RSTS-DMI VC1 Resource Status Register
192
DMIVCPRCAP-DMI Vcp Resource Capability Register
192
DMIVCPRCTL-DMI Vcp Resource Control Register
193
DMIVCPRSTS-DMI Vcp Resource Status Register
194
DMIESD-DMI Element Self Description Register
195
DMILE1A-DMI Link Entry 1 Address Register
196
DMILE1D-DMI Link Entry 1 Description Register
196
DMILE2A-DMI Link Entry 2 Address Register
197
DMILE2D-DMI Link Entry 2 Description Register
197
LCAP-Link Capabilities Register
198
LCTL-Link Control Register
199
LSTS-DMI Link Status Register
200
LCTL2-Link Control 2 Register
201
LSTS2-Link Status 2 Register
203
MCHBAR Registers in Memory Controller - Channel 0
204
Pm_Pdwn_Config_C0-Power-Down Configuration Register
204
MCHBAR Registers in Memory Controller - Channel 0 Register Address Map
204
TC_RFP_C0-Refresh Parameters Register
205
TC_RFTP_C0-Refresh Parameters Register
205
MCHBAR Registers in Memory Controller - Channel 1
206
Pm_Pdwn_Config_C1-Power-Down Configuration Register
206
MCHBAR Registers in Memory Controller - Channel 1 Register Address Map
206
TC_RFP_C1-Refresh Parameters Register
207
TC_RFTP_C1-Refresh Timing Parameters Register
207
MCHBAR Registers in Memory Controller - Integrated Memory Peripheral Hub (IMPH)
208
CRDTCTL3-Credit Control 3 Register
208
MCHBAR Registers in Memory Controller - Integrated Memory Peripheral Hub
208
MCHBAR Registers in Memory Controller - Common
209
MAD_CHNL-Address Decoder Channel Configuration Register
209
MCHBAR Registers in Memory Controller - Common Register Address Map
209
Mad_Dimm_Ch0-Address Decode Channel 0 Register
210
Mad_Dimm_Ch1 - Address Decode Channel 1 Register
211
Pm_Sref_Config-Self Refresh Configuration Register
212
Memory Controller MMIO Registers Broadcast Group
213
Pm_Pdwn_Config-Power-Down Configuration Register
213
Memory Controller MMIO Registers Broadcast Group Register Address Map
213
PM_CMD_PWR-Power Management Command Power Register
214
Pm_Bw_Limit_Config-BW Limit Configuration Register
214
Integrated Graphics Vtd Remapping Engine Registers
215
Integrated Graphics Vtd Remapping Engine Register Address Map
215
VER_REG-Version Register
216
CAP_REG-Capability Register
217
ECAP_REG-Extended Capability Register
220
GCMD_REG-Global Command Register
222
GSTS_REG-Global Status Register
225
RTADDR_REG-Root-Entry Table Address Register
226
CCMD_REG-Context Command Register
227
FSTS_REG-Fault Status Register
229
FECTL_REG-Fault Event Control Register
231
FEDATA_REG-Fault Event Data Register
232
FEADDR_REG-Fault Event Address Register
232
FEUADDR_REG-Fault Event Upper Address Register
232
AFLOG_REG-Advanced Fault Log Register
233
PMEN_REG-Protected Memory Enable Register
234
PLMBASE_REG-Protected Low-Memory Base Register
235
PLMLIMIT_REG-Protected Low-Memory Limit Register
236
PHMBASE_REG-Protected High-Memory Base Register
237
PHMLIMIT_REG-Protected High-Memory Limit Register
238
IQH_REG-Invalidation Queue Head Register
239
IQT_REG-Invalidation Queue Tail Register
239
IQA_REG-Invalidation Queue Address Register
240
ICS_REG-Invalidation Completion Status Register
240
IECTL_REG-Invalidation Event Control Register
241
IEDATA_REG-Invalidation Event Data Register
242
IEUADDR_REG-Invalidation Event Upper Address Register
242
IRTA_REG-Interrupt Remapping Table Address Register
243
IVA_REG-Invalidate Address Register
244
IOTLB_REG-IOTLB Invalidate Register
245
FRCDL_REG-Fault Recording Low Register
247
FRCDH_REG-Fault Recording High Register
248
VTPOLICY-DMA Remap Engine Policy Control Register
249
PCU MCHBAR Registers
250
PCU MCHBAR Register Address Map
250
MEM_TRML_ESTIMATION_CONFIG-Memory Thermal Estimation Configuration Register
251
MEM_TRML_THRESHOLDS_CONFIG-Memory Thermal Thresholds Configuration Register
252
MEM_TRML_STATUS_REPORT-Memory Thermal Status Report Register
253
MEM_TRML_TEMPERATURE_REPORT-Memory Thermal Temperature Report Register
254
MEM_TRML_INTERRUPT-Memory Thermal Interrupt Register
254
GT_PERF_STATUS-GT Performance Status Register
255
RP_STATE_CAP-RP State Capability Register
255
SSKPD-Sticky Scratchpad Data Register
256
Pxpepbar
258
EPVC0RCTL-EP VC 0 Resource Control Register
258
Default PEG/DMI Vtd Remapping Engine Registers
259
Default PEG/DMI Vtd Remapping Engine Register Address Map
259
VER_REG-Version Register
260
CAP_REG-Capability Register
261
ECAP_REG-Extended Capability Register
264
GCMD_REG-Global Command Register
266
GSTS_REG-Global Status Register
269
RTADDR_REG-Root-Entry Table Address Register
270
CCMD_REG-Context Command Register
271
FSTS_REG-Fault Status Register
273
FECTL_REG-Fault Event Control Register
275
FEDATA_REG-Fault Event Data Register
276
FEADDR_REG-Fault Event Address Register
276
FEUADDR_REG-Fault Event Upper Address Register
276
AFLOG_REG-Advanced Fault Log Register
277
PMEN_REG-Protected Memory Enable Register
278
PLMBASE_REG-Protected Low-Memory Base Register
279
PLMLIMIT_REG-Protected Low-Memory Limit Register
280
PHMBASE_REG-Protected High-Memory Base Register
281
PHMLIMIT_REG-Protected High-Memory Limit Register
282
IQH_REG-Invalidation Queue Head Register
283
EG-Invalidation Queue Tail Register
283
IQA_REG-Invalidation Queue Address Register
284
ICS_REG-Invalidation Completion Status Register
284
IECTL_REG-Invalidation Event Control Register
285
IEDATA_REG-Invalidation Event Data Register
286
IEADDR_REG-Invalidation Event Address Register
286
IEUADDR_REG-Invalidation Event Upper Address Register
287
IRTA_REG-Interrupt Remapping Table Address Register
287
IVA_REG-Invalidate Address Register
288
IOTLB_REG-IOTLB Invalidate Register
289
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INTEL Core i7 Desktop Series Datasheet (172 pages)
Brand:
INTEL
| Category:
Computer Hardware
| Size: 1.75 MB
Table of Contents
Table of Contents
3
Revision History
10
1 Introduction
11
2Nd Generation Intel Platform
12
Processor Feature Details
13
Supported Technologies
13
Interfaces
13
System Memory Support
13
PCI Express
14
Pcie Supported Configurations in Mobile Products
14
Direct Media Interface (DMI)
15
Platform Environment Control Interface (PECI)
16
Processor Graphics
16
Embedded Displayport* (Edp*)
17
Intel ® Flexible Display Interface (Intel ® FDI)
17
Power Management Support
17
DMI
17
Memory Controller
17
PCI Express
17
Processor Core
17
System
17
Processor Graphics Controller
18
Thermal Management Support
18
Package
18
Terminology
18
Related Documents
21
2 Interfaces
23
System Memory Interface
23
System Memory Technology Supported
23
Supported SO-DIMM Module Configurations 1,2
23
System Memory Timing Support
24
System Memory Organization Modes
24
Dual-Channel Mode - Intel ® Flex Memory Technology Mode
24
Single-Channel Mode
24
DDR3 System Memory Timing Support
24
Rules for Populating Memory Slots
25
Intel ® Flex Memory Technology Operation
25
Fma)
26
Just-In-Time Command Scheduling
26
Command Overlap
26
Out-Of-Order Scheduling
26
Memory Type Range Registers (Mtrrs) Enhancement
26
Data Scrambling
26
DRAM Clock Generation
26
PCI Express* Interface
27
PCI Express* Architecture
27
PCI Express* Layering Diagram
27
Transaction Layer
28
Data Link Layer
28
Physical Layer
28
Packet Flow through the Layers
28
PCI Express* Configuration Mechanism
29
PCI Express Graphics
29
PCI Express* Related Register Structures in the Processor
29
PCI Express Lanes Connection
30
Direct Media Interface (DMI)
30
DMI Error Flow
30
Processor/Pch Compatibility Assumptions
30
Pcie Typical Operation 16 Lanes Mapping
30
DMI Link down
31
Processor Graphics Controller (GT)
31
Processor Graphics Controller Unit Block Diagram
31
3D and Video Engines for Graphics Processing
32
3D Engine Execution Units
32
3D Pipeline
32
Engine
33
Video Engine
33
Display Planes
34
Processor Graphics Display
34
Processor Display Block Diagram
34
Display Pipes
35
Display Ports
35
Embedded Displayport (Edp)
35
Intel Flexible Display Interface
35
Multi-Graphics Controller Multi-Monitor Support
36
Platform Environment Control Interface (PECI)
36
Interface Clocking
36
Internal Clocking Requirements
36
Reference Clock
36
3 Technologies
37
Intel Virtualization Technology
37
Intel VT-X Objectives
37
Intel VT-X Features
38
Intel VT-D Objectives
38
Intel VT-D Features
39
Intel
39
Intel Trusted Execution Technology (Intel TXT)
40
Intel Hyper-Threading Technology
40
Intel Turbo Boost Technology
41
Intel Turbo Boost Technology Frequency
41
Intel Advanced Vector Extensions (AVX)
42
Intel Turbo Boost Technology Graphics Frequency
42
Advanced Encryption Standard New Instructions (AES-NI)
42
PCLMULQDQ Instruction
43
Intel ® 64 Architecture X2Apic
43
4 Power Management
45
ACPI States Supported
45
System States
45
Processor Core/Package Idle States
45
Processor Core/Package State Support
45
Integrated Memory Controller States
46
Pcie Link States
46
DMI States
46
Processor Graphics Controller States
46
Interface State Combinations
47
G, S, and C State Combinations
47
D, S, and C State Combination
47
Processor Core Power Management
48
Enhanced Intel ® Speedstep ® Technology
48
Low-Power Idle States
48
Idle Power Management Breakdown of the Processor Cores
49
Thread and Core C-State Entry and Exit
49
Requesting Low-Power Idle States
50
Coordination of Thread Power States at the Core Level
50
P_Lvlx to MWAIT Conversion
50
Core C-States
51
Core C0 State
51
Core C1/C1E State
51
Core C3 State
51
Core C6 State
51
Core C7 State
51
C-State Auto-Demotion
52
Package C-States
52
Package C0
53
Package C-State Entry and Exit
53
Coordination of Core Power States at the Package Level
53
Package C1/C1E
54
Package C3 State
54
Package C6 State
54
Package C7 State
55
Dynamic L3 Cache Sizing
55
IMC Power Management
55
Disabling Unused System Memory Outputs
55
DRAM Power Management and Initialization
56
Conditional Self-Refresh
57
Initialization Role of CKE
57
DRAM I/O Power Management
58
Dynamic Power-Down Operation
58
Pcie* Power Management
58
DMI Power Management
58
Targeted Memory State Conditions
58
Graphics Power Management
59
Graphics Performance Modulation Technology(GPMT)
59
Graphics Render C-State
59
Intel
59
Intel Smart 2D Display Technology (Intel S2DDT)
59
Automatic Display Brightness (ADB)
60
Display Power Savings Technology 6.0 (DPST)
60
Intel Graphics Dynamic Frequency
60
Seamless Display Refresh Rate Switching Technology (SDRRST)
61
Thermal Power Management
61
5 Thermal Management
63
Thermal Design Power (TDP) and Junction Temperature (Tj)
63
Thermal Considerations
63
Intel ® Turbo Boost Technology Power Control and Reporting
64
Package Power Control
65
Power Plane Control
65
Turbo Time Parameter
65
Thermal and Power Specifications
66
TDP Specifications
67
Junction Temperature Specification
67
Package Turbo Parameters
68
Idle Power Specifications
69
Thermal Management Features
70
Adaptive Thermal Monitor
70
Processor Package Thermal Features
70
Frequency and Voltage Ordering
71
Digital Thermal Sensor
72
PROCHOT# Signal
73
Processor Core Specific Thermal Features
75
On-Demand Mode
75
Fan Speed Control with Digital Thermal Sensor
76
Memory Controller Specific Thermal Features
76
Platform Environment Control Interface (PECI)
76
Programmable Trip Points
76
6 Signal Description
77
Signal Description Buffer Types
77
System Memory Interface
78
Memory Channel a
78
Memory Reference and Compensation
79
Memory Channel B
79
Reset and Miscellaneous Signals
80
PCI Express* Based Interface Signals
80
PCI Express* Graphics Interface Signals
80
Embedded Displayport (Edp)
81
Intel ® Flexible Display Interface Signals
81
DMI
81
Embedded Display Port Signals
81
Intel® Flexible Display Interface
81
DMI - Processor to PCH Serial Interface
81
PLL Signals
82
TAP Signals
82
Error and Thermal Protection
83
Power Sequencing
83
Processor Power Signals
84
Sense Pins
84
Ground and NCTF
85
Future Compatibility
85
Processor Internal Pull Up/Pull down
85
7 Electrical Specifications
87
Power and Ground Pins
87
Decoupling Guidelines
87
Voltage Rail Decoupling
87
PLL Power Supply
87
Voltage Identification (VID)
88
IMVP7 Voltage Identification Definition
89
Reserved or Unused Signals
92
System Agent (SA)
92
CC VID
92
VCCSA_VID Configuration
92
Signal Groups
93
Signal Groups1
93
Test Access Port (TAP) Connection
95
Storage Condition Specifications
95
DC Specifications
96
Storage Condition Ratings
96
Voltage and Current Specifications
97
Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications
97
Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications
98
Memory Controller (VDDQ) Supply DC Voltage and Current Specifications
99
System Agent (VCCSA) Supply DC Voltage and Current Specifications
99
Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications
99
Processor Graphics (VAXG) Supply DC Voltage and Current Specifications
100
DDR3 Signal Group DC Specifications
101
Control Sideband and TAP Signal Group DC Specifications
102
PCI Express DC Specifications
102
Platform Environmental Control Interface (PECI) DC Specifications
103
PECI Bus Architecture
103
Edp DC Specifications
103
PECI DC Characteristics
104
Example for PECI Host-Clients Connection
104
PECI DC Electrical Limits
104
Input Device Hysteresis
105
8 Processor Pin and Signal Information
107
Processor Pin as Signments
107
Rpga988B (Socket-G2) Pinmap (Top View, Upper-Left Quadrant)
108
Rpga988B (Socket-G2) Pinmap (Top View, Upper-Right Quadrant)
109
Rpga988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant)
110
Rpga988B (Socket-G2) Pinmap (Top View, Lower-Right Quadrant)
111
Rpga988B Processor Pin List by Pin Name
112
BGA1224 Ballmap (Top View, Upper-Left Quadrant)
123
BGA1224 Ballmap (Top View, Upper-Right Quadrant)
124
BGA1224 Ballmap (Top View, Lower-Left Quadrant)
125
BGA1224 Ballmap (Top View, Lower-Right Quadrant)
126
BGA1224 Processor Ball List by Ball Name
127
BGA1023 Ballmap (Top View, Upper-Left Quadrant)
142
BGA1023 Ballmap (Top View, Upper-Right Quadrant)
143
BGA1023 Ballmap (Top View, Lower-Left Quadrant)
144
BGA1023 Ballmap (Top View, Lower-Right Quadrant)
145
BGA1023 Processor Ball List by Ball Name
146
Package Mechanical Information
157
Processor Rpga988B 2C (GT2) Mechanical Package (Sheet 1 of 2)
157
Processor Rpga988B 2C (GT2) Mechanical Package (Sheet 2 of 2)
158
Processor Rpga988B 4C (GT2) Mechanical Package (Sheet 1 of 2)
159
Processor Rpga988B 4C (GT2) Mechanical Package (Sheet 2 of 2)
160
Processor BGA1023 2C (GT2) Mechanical Package (Sheet 1 of 2)
161
Processor BGA1023 2C (GT2) Mechanical Package (Sheet 2 of 2)
162
Processor BGA1224 4C (GT2) Mechanical Package (Sheet 1 of 2)
163
Processor BGA1224 4C (GT2) Mechanical Package (Sheet 2 of 2)
164
Processor Rpga988B 2C (GT1) Mechanical Package (Sheet 1 of 2)
165
Processor Rpga988B 2C (GT1) Mechanical Package (Sheet 2 of 2)
166
Processor BGA1023 2C (GT1) Mechanical Package (Sheet 1 of 2)
167
Processor BGA1023 2C (GT1) Mechanical Package (Sheet 2 of 2)
168
9 DDR Data Swizzling
169
DDR Data Swizzling Table - Channel a
170
DDR Data Swizzling Table - Channel B
171
INTEL Core i7 Desktop Series Datasheet (110 pages)
2nd Generation Core Processor Family Desktop
Brand:
INTEL
| Category:
Computer Hardware
| Size: 0.78 MB
Table of Contents
Table of Contents
3
Revision History
8
1 Introduction
9
2Nd Generation Intel ® Core™ Processor Family Desktop Platform
10
Processor Feature Details
11
Supported Technologies
11
Interfaces
11
System Memory Support
11
PCI Express
12
Pcie Supported Configurations in Desktop Products
12
Direct Media Interface (DMI)
13
Platform Environment Control Interface (PECI)
14
Processor Graphics
14
Intel ® Flexible Display Interface (Intel ® FDI)
14
Power Management Support
15
DMI
15
Memory Controller
15
PCI Express
15
Processor Core
15
Processor Graphics Controller
15
System
15
Thermal Management Support
15
Package
16
Terminology
16
Related Documents
18
2 Interfaces
19
System Memory Interface
19
System Memory Technology Supported
19
Supported UDIMM Module Configurations
19
System Memory Timing Support
20
Supported SO-DIMM Module Configurations (AIO Only)
20
DDR3 System Memory Timing Support
20
System Memory Organization Modes
21
Dual-Channel Mode - Intel ® Flex Memory Technology Mode
21
Single-Channel Mode
21
Intel ® Flex Memory Technology Operation
21
Rules for Populating Memory Slots
22
Fma)
22
Just-In-Time Command Scheduling
22
Command Overlap
23
Data Scrambling
23
Memory Type Range Registers (Mtrrs) Enhancement
23
Out-Of-Order Scheduling
23
PCI Express* Interface
24
PCI Express* Architecture
24
PCI Express* Layering Diagram
24
Transaction Layer
25
Data Link Layer
25
Physical Layer
25
Packet Flow through the Layers
25
PCI Express* Configuration Mechanism
26
PCI Express* Port
26
PCI Express* Related Register Structures in the Processor
26
PCI Express Lanes Connection
27
Direct Media Interface (DMI)
27
DMI Error Flow
27
Processor/Pch Compatibility Assumptions
27
Pcie Typical Operation 16 Lanes Mapping
27
DMI Link down
28
Processor Graphics Controller (GT)
28
Processor Graphics Controller Unit Block Diagram
28
And Video Engines for Graphics Processing
29
3D Engine Execution Units
29
Pipeline
29
Engine
30
Video Engine
30
Display Planes
31
Processor Graphics Display
31
Processor Display Block Diagram
31
Display Pipes
32
Display Ports
32
Intel Flexible Display Interface
32
Multi-Graphics Controller Multi-Monitor Support
32
Platform Environment Control Interface (PECI)
33
Interface Clocking
33
Internal Clocking Requirements
33
Reference Clock
33
3 Technologies
35
Intel Virtualization Technology
35
Intel VT-X Objectives
35
Intel VT-X Features
36
Intel VT-D Objectives
36
Intel VT-D Features
37
Intel
37
Intel Trusted Execution Technology (Intel TXT)
38
Intel Hyper-Threading Technology
38
Intel Turbo Boost Technology
39
Intel Turbo Boost Technology Frequency
39
Intel
39
Intel Advanced Vector Extensions (AVX)
40
Advanced Encryption Standard New Instructions (AES-NI)
40
PCLMULQDQ Instruction
40
Intel ® 64 Architecture X2Apic
41
4 Power Management
43
ACPI States Supported
43
System States
43
Processor Core/Package Idle States
43
Processor Core/Package State Support
43
Integrated Memory Controller States
44
Pcie Link States
44
DMI States
44
Processor Graphics Controller States
44
Interface State Combinations
45
Processor Core Power Management
45
Enhanced Intel ® Speedstep ® Technology
45
G, S and C State Combinations
45
Low-Power Idle States
46
Idle Power Management Breakdown of the Processor Cores
46
Thread and Core C-State Entry and Exit
46
Requesting Low-Power Idle States
47
Coordination of Thread Power States at the Core Level
47
P_Lvlx to MWAIT Conversion
47
Core C-States
48
C-State Auto-Demotion
48
Core C0 State
48
Core C1/C1E State
48
Core C3 State
48
Core C6 State
48
Package C-States
49
Package C0
50
Package C-State Entry and Exit
50
Coordination of Core Power States at the Package Level
50
Package C1/C1E
51
Package C3 State
51
Package C6 State
51
IMC Power Management
52
Disabling Unused System Memory Outputs
52
DRAM Power Management and Initialization
52
Conditional Self-Refresh
54
DRAM I/O Power Management
54
Dynamic Power-Down Operation
54
Initialization Role of CKE
54
Pcie* Power Management
54
DMI Power Management
55
Graphics Power Management
55
Graphics Render C-State
55
Intel Smart 2D Display Technology (Intel S2DDT)
55
Intel® Graphics Performance Modulation Technology(GPMT)
55
Intel® Rapid Memory Power Management (RMPM) (also Know as Cxsr)
55
Intel Graphics Dynamic Frequency
56
Thermal Power Management
56
5 Thermal Management
57
6 Signal Description
59
Signal Description Buffer Types
59
System Memory Interface
60
Memory Channel a
60
Memory Reference and Compensation
61
Memory Channel B
61
Reset and Miscellaneous Signals
62
PCI Express* Based Interface Signals
63
Intel ® Flexible Display Interface Signals
63
PCI Express* Graphics Interface Signals
63
Intel ® Flexible Display Interface
63
DMI
64
PLL Signals
64
TAP Signals
64
DMI - Processor to PCH Serial Interface
64
Error and Thermal Protection
65
Power Sequencing
65
Processor Power Signals
66
Sense Pins
66
Ground and NCTF
66
Processor Internal Pull Up/Pull down
67
7 Electrical Specifications
69
Power and Ground Lands
69
Decoupling Guidelines
69
Voltage Rail Decoupling
69
Processor Clocking (BCLK[0], BCLK#[0])
70
PLL Power Supply
70
VCC Voltage Identification (VID)
70
VR 12.0 Voltage Identification Definition
71
System Agent (SA) VCC VID
74
Reserved or Unused Signals
74
VCCSA_VID Configuration
74
Signal Groups
75
Signal Groups 1
75
Test Access Port (TAP) Connection
76
Storage Conditions Specifications
77
Storage Condition Ratings
77
DC Specifications
78
Voltage and Current Specifications
78
Processor Core Active and Idle Mode DC Voltage and Current Specifications
78
Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications
80
Processor Graphics VID Based (VAXG) Supply DC Voltage and Current Specifications
81
DDR3 Signal Group DC Specifications
81
Control Sideband and TAP Signal Group DC Specifications
82
Pcie DC Specifications
83
Platform Environmental Control Interface (PECI) DC Specifications
84
PECI Bus Architecture
84
Example for PECI Host-Clients Connection
84
DC Characteristics
85
Input Device Hysteresis
85
PECI DC Electrical Limits
85
8 Processor Pin and Signal Information
87
Processor Pin Assignments
87
Socket Pinmap (Top View, Upper-Left Quadrant)
88
Socket Pinmap (Top View, Upper-Right Quadrant)
89
Socket Pinmap (Top View, Lower-Left Quadrant)
90
Socket Pinmap (Top View, Lower-Right Quadrant)
91
Processor Pin List by Pin Name
92
9 DDR Data Swizzling
107
DDR Data Swizzling Table - Channel a
108
DDR Data Swizzling Table - Channle B
109
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