Mlimit6-Memory Limit Address Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.10.16 MLIMIT6—Memory Limit Address Register
This register controls the processor to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE  address  MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode, address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1 MB
aligned memory block.
Note: Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express-G address ranges (typically, where control/status memory-
mapped I/O data structures of the graphics controller will reside) and PMBASE and
PMLIMIT are used to map prefetchable address ranges (typically, graphics local
memory). This segregation allows application of USWC space attribute to be performed
in a true plug-and-play manner to the prefetchable address range for improved
processor-PCI Express memory access performance.
Note: Configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges
(that is, prevent overlap with each other and/or with the ranges covered with the main
memory). There is no provision in the processor hardware to enforce prevention of
overlap and operations of the system in the case of overlap are not ensured.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:4
3:0
154
0/6/0/PCI
22–23h
0000h
RW
16 bits
0h
Reset RST/
Attr
Value PWR
RW 000h Uncore
RO 0h
Processor Configuration Registers
Description
Memory Address Limit (MLIMIT)
This field corresponds to A[31:20] of the uppe r limit of the address
range passed to PCI Express-G.
Reserved
Datasheet, Volume 2