Igd Frame Buffer Accesses; Igd Vga I/O Mapping - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Accesses to the VGA memory range are directed to IGD depend on the configuration.
The configuration is specified by:
• Internal Graphics Controller in Device 2 is enabled (DEVEN.D2EN bit 4)
• Internal Graphics VGA in Device 0, function 0 is enabled through register GGC bit 1.
• IGD memory accesses (PCICMD2 04 – 05h, MAE bit 1) in Device 2 configuration
space are enabled.
• VGA Compatibility Memory accesses (VGA Miscellaneous output Register - MSR
Register, bit 1) are enabled.
• Software sets the proper value for VGA Memory Map Mode Register (VGA GR06
Register, bits 3-2). See
Table 2-4.

IGD Frame Buffer Accesses

Mem Access
GR06(3:2)
00
01
10
11
Note: Additional qualification within IGD comprehends internal MDA support. The VGA and
MDA enabling bits detailed below control segments not mapped to IGD.
VGA I/O range is defined as addresses where A[15:0] are in the ranges 03B0h to
03BBh, and 03C0h to 03DFh. VGA I/O accesses are directed to IGD depends on the
following configuration.
• Internal Graphics Controller in Device 2 is enabled through register DEVEN.D2EN
bit 4.
• Internal Graphics VGA in Device 0 function 0 is enabled through register GGC bit 1.
• IGD I/O accesses (PCICMD2 04 – 05h, IOAE bit 0) in Device 2 are enabled.
• VGA I/O decodes for IGD uses 16 address bits (15:0) there is no aliasing. Note that
this is different when compared to a bridge device (Device 1) that used only 10
address bits (A 9:0) for VGA I/O decode.
• VGA I/O input/output address select (VGA Miscellaneous output Register – MSR
Register, bit 0) used to select mapping of I/O access as defined in
Table 2-5.

IGD VGA I/O Mapping

I/O Access

MSRb0
0
1
Note: Additional qualification within IGD comprehends internal MDA support. The VGA and
MDA enabling bits detailed below control ranges not mapped to IGD.
42
Table 2-4 for translations.
A0000h–AFFFFh
IGD
IGD
PCI Express Bridge or
DMI Interface
PCI Express Bridge or
DMI Interface
3CX 3DX
PCI Express Bridge or DMI
IGD
Interface
IGD IGD
Processor Configuration Registers
B0000h–B7FFFh
MDA
IGD
PCI Express Bridge or DMI
Interface
IGD
PCI Express Bridge or DMI
Interface
3B0–3BB
IGD
PCI Express Bridge or
DMI Interface
B8000h–BFFFFh
IGD
PCI Express Bridge or DMI
Interface
PCI Express Bridge or DMI
Interface
IGD
Table 2-5.
3BC–3BF
PCI Express Bridge or
DMI Interface
PCI Express Bridge or
DMI Interface
Datasheet, Volume 2