Fsts_Reg-Fault Status Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.18.8 FSTS_REG—Fault Status Register
This register indicates the various error status.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:16
15:8
7:7
6
5
4
3
Datasheet, Volume 2
0/0/0/GFXVTBAR
34–37h
00000000h
RO, ROS-V, RW1CS
32 bits
00000h
Reset RST/
Attr
Value PWR
RO 0h
Powerg
ROS-V 00h
ood
RO 0h
RO 0b Uncore
RO 0b Uncore
Powerg
RW1CS 0b
ood
RO 0b Uncore
Description
Reserved
Fault Record Index (FRI)
This field is valid only when the PPF field is set.
The FRI field indicates the index (from base) of the fault recording
register to which the first pending fault was recorded when the PPF
field was Set by hardware.
The value read from this field is undefined when the PPF field is
clear.
Reserved
Invalidation Time-out Error (ITE)
Hardware detected a Device-IOTLB invalidation completion time-
out. At this time, a fault event may be generated based on the
programming of the Fault Event Control register.
Hardware implementations not supporting device Device-IOTLBs
implement this bit as RsvdZ.
Invalidation Completion Error (ICE)
Hardware received an unexpected or invalid Device-IOTLB
invalidation completion. This could be due to either an invalid ITag
or invalid source-id in an invalidation completion response. At this
time, a fault event may be generated based on the programming of
the Fault Event Control register.
Hardware implementations not supporting Device-IOTLBs
implement this bit as RsvdZ.
Invalidation Queue Error (IQE)
Hardware detected an error associated with the invalidation queue.
This could be due to either a hardware error while fetching a
descriptor from the invalidation queue, or hardware detecting an
erroneous or invalid descriptor in the invalidation queue. At this
time, a fault event may be generated based on the programming of
the Fault Event Control register.
Hardware implementations not supporting queued invalidations
implement this bit as RsvdZ.
Advanced Pending Fault (APF)
When this bit is 0, hardware sets this bit when the first fault record
(at index 0) is written to a fault log. At this time, a fault event is
generated based on the programming of the Fault Event Control
register.
Software writing 1 to this field clears it. Hardware implementations
not supporting advanced fault logging implement this bit as RsvdZ.
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