Pmbaseu1-Prefetchable Memory Base Address Upper Register; Pmlimitu1-Prefetchable Memory Limit Address Upper Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.6.19 PMBASEU1—Prefetchable Memory Base Address Upper
Register
The functionality associated with this register is present in the PEG design
implementation. This register in conjunction with the corresponding Upper Base
Address register controls the processor to PCI Express-G prefetchable memory access
routing based on the following formula:
PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Base Address register are
read/write and correspond to address bits A[38:32] of the 39-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:0
2.6.20 PMLIMITU1—Prefetchable Memory Limit Address Upper
Register
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE  address  PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Limit Address register are
read/write and correspond to address bits A[38:32] of the 39-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block.
Note: Prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (that is, prefetchable) from the processor perspective.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:0
98
0/1/0–2/PCI
28–2Bh
00000000h
RW
32 bits
Reset RST/
Attr
Value PWR
00000000
RW Uncore
h
0/1/0–2/PCI
2C–2Fh
00000000h
RW
32 bits
Reset RST/
Attr
Value PWR
RW 00000000h Uncore
Processor Configuration Registers
Description
Prefetchable Memory Base Address (PMBASEU)
This field corresponds to A[63:32] of the lower limit of the
prefetchable memory range that will be passed to PCI Express-G.
Description
Prefetchable Memory Address Limit (PMLIMITU)
This field corresponds to A[63:32] of the upper limit of the
prefetchable Memory range that will be passed to PCI Express-G.
Datasheet, Volume 2