Dmipvcctl-Dmi Port Vc Control Register; Dmivc0Rcap-Dmi Vc0 Resource Capability Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.12.4 DMIPVCCTL—DMI Port VC Control Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:4
3:1
0
2.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:24
23:23
22:16
15
14:8
7:0
188
0/0/0/DMIBAR
C–Dh
0000h
RW, RO
16 bits
000h
Reset RST/
Attr
Value PWR
RO 0h
RW 000b Uncore
RO 0b Uncore
0/0/0/DMIBAR
10–13h
00000001h
RO
32 bits
00h
Reset RST/
Attr
Value PWR
RO 00h Uncore
RO 0h
RO 00h Uncore
RO 0b Uncore
RO 0h
RO 01h Uncore
Processor Configuration Registers
Description
Reserved
VC Arbitration Select (VCAS)
This field will be programmed by software to the only possible
value as indicated in the VC Arbitration Capability field.
The value 000b when written to this field will indicate the VC
arbitration scheme is hardware fixed (in the root complex). This
field cannot be modified when more than one VC in the LPVC group
is enabled.
000 = Hardware fixed arbitration scheme (such as, Round Robin)
Others = Reserved
See the PCI express specification for more details.
Reserved for Load VC Arbitration Table (LVCAT)
Description
Reserved for Port Arbitration Table Offset (PATO)
Reserved
Reserved for Maximum Time Slots (MTS)
Reject Snoop Transactions (REJSNPT)
0 = Transactions with or without the No Snoop bit set within the
TLP header are allowed on this VC.
1 = Any transaction for which the No Snoop attribute is applicable
but is not set within the TLP Header will be rejected as an
Unsupported Request.
Reserved
Port Arbitration Capability (PAC)
Having only bit 0 set indicates that the only supported arbitration
scheme for this VC is non-configurable hardware-fixed.
Datasheet, Volume 2