Pvccap2-Port Vc Capability Register 2; Pvcctl-Port Vc Control Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.7.2 PVCCAP2—Port VC Capability Register 2
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:24
23:8
7:0
2.7.3 PVCCTL—Port VC Control Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:4
3:1
0
124
0/1/0–2/MMR
108–10Bh
00000000h
RO
32 bits
0000h
Reset RST/
Attr
Value PWR
RO 00h Uncore
RO 0h
RO 00h Uncore
0/1/0–2/MMR
10C–10Dh
0000h
RW, RO
16 bits
000h
Reset RST/
Attr
Value PWR
RO 0h
RW 000b Uncore
RO 0b Uncore
Processor Configuration Registers
Description
VC Arbitration Table Offset (VCATO)
Indicates the location of the VC Arbitration Table. This field
contains the zero-based offset of the table in DQWORDS (16 bytes)
from the base address of the Virtual Channel Capability Structure.
A value of 0 indicates that the table is not present (due to fixed VC
priority).
Reserved
Reserved for VC Arbitration Capability (VCAC)
Description
Reserved
VC Arbitration Select (VCAS)
This field will be programmed by software to the only possible
value as indicated in the VC Arbitration Capability field. Since there
is no other VC supported than the default, this field is reserved.
Reserved for Load VC Arbitration Table (VCARB)
Used for software to update the VC Arbitration Table when VC
arbitration uses the VC Arbitration Table. As a VC Arbitration Table
is never used by this component this field will never be used.
Datasheet, Volume 2