Memory Re-Claim Background; Indirect Accesses To Mchbar Registers - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.3.4.1

Memory Re-claim Background

The following are examples of Memory Mapped IO devices that are typically located
below 4 GB:
• High
• TSEG
• GFX
• GTT
• XAPIC
• Local
• MSI Interrupts
• Mbase/Mlimit
• Pmbase/PMlimit
• Memory Mapped IO space that supports only 32B addressing
The processor provides the capability to re-claim the physical memory overlapped by
the Memory Mapped IO logical address spac e. The processor re-maps physical memory
from the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an
equivalent sized logical address range located just below the Manageability Engine's
stolen memory.
2.3.4.2

Indirect Accesses to MCHBAR Registers

This access is similar to prior chipsets, MCHBAR registers can be indirectly accessed
using:
• Direct MCHBAR access decode
1. Cycle to memory from processor
Hits MCHBAR base, AND
2.
MCHBAR is enabled, AND
3.
Within MMIO space (above and below 4 GB)
4.
• GTTMMADR (10000h–13FFFh) range -> MCHBAR decode
Cycle to memory from processor, AND
1.
Device 2 (IGD) is enabled, AND
2.
Memory accesses for device 2 is enabled, AND
3.
Targets GFX MMIO Function 0, AND
4.
MCHBAR is enabled or cycle is a read. If MCHBAR is disabled, only read
5.
access is allowed.
• MCHTMBAR
Cycle to memory from processor, AND
1.
AND Targets MCHTMBAR base
2.
• IOBAR -> GTTMMADR -> MCHBAR.
Follows IOBAR rules. See GTTMMADR information above as well.
Datasheet, Volume 2
B I OS
s tolen
s tolen
A P IC
(Thermal Monitor)
- > MCHBAR
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