Mc-Message Control Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.10.30 MC—Message Control Register
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
assured to be serviced. If all of them must be serviced, the device must not generate
the same message again until the driver services the earlier one.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:8
7
6:4
3:1
0
166
0/6/0/PCI
92–93h
0000h
RO, RW
16 bits
00h
Reset RST/
Attr
Value PWR
RO 0h
RO 0b Uncore
RW 000b Uncore
RO 000b Uncore
RW 0b Uncore
Processor Configuration Registers
Description
Reserved
64-bit Address Capable (B64AC)
Hardwired to 0 to indicate that the function does not implement
the upper 32 bits of the Message Address register and is incapable
of generating a 64-bit memory address.
This may need to change in future implementations when
addressable system memory exceeds the 32b/4 GB limit.
Multiple Message Enable (MME)
System software programs this field to indicate the actual number
of messages allocated to this device. This number will be equal to
or less than the number actually requested.
The encoding is the same as for the MMC field below.
Multiple Message Capable (MMC)
System software reads this field to determine the number of
messages being requested by this device. Encodings for the
number of messages requested are:
000 = 1
All of the following are reserved in this implementation:
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = Reserved
111 =Reserved
MSI Enable (MSIEN)
Controls the ability of this device to generate MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME messages. INTA
will not be generated and INTA Status (PCISTS1[3]) will not
be set.
Datasheet, Volume 2