Dmile1D-Dmi Link Entry 1 Description Register; Dmile1A-Dmi Link Entry 1 Address Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.12.15 DMILE1D—DMI Link Entry 1 Description Register
This register provides the first part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:24
23:16
15:2
1
0
2.12.16 DMILE1A—DMI Link Entry 1 Address Register
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:12
11:0
196
0/0/0/DMIBAR
50–53h
00000000h
RW-O, RO
32 bits
0000h
Reset RST/
Attr
Value PWR
RW-O 00h Uncore
RW-O 00h Uncore
RO 0h
RO 0b Uncore
RW-O 0b Uncore
0/0/0/DMIBAR
58–5Bh
00000000h
RW-O
32 bits
000h
Reset RST/
Attr
Value PWR
RW-O 00000h Uncore
RO 0h
Processor Configuration Registers
Description
Target Port Number (TPN)
This field specifies the port number associated with the element
targeted by this link entry (egress port of PCH). The target port
number is with respect to the component that contains this
element as specified by the target component ID.
This can be programmed by BIOS, but t he Reset Value will likely be
correct because the DMI RCRB in the PCH will likely be associated
with the default egress port for the PCH meaning it will be assigned
port number 0.
Target Component ID (TCID)
This field identifies the physical component that is targeted by this
link entry.
BIOS Requirement: Must be initialized according to guidelines in
the PCI Express* Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
Reserved
Link Type (TXTYP)
This bit indicates that the link points to memory-mapped space (for
RCRB).
The link address specifies the 64-bit base address of the target
RCRB.
Link Valid (LV)
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Description
Link Address (LA)
Memory mapped base address of the RCRB that is the target
element (egress port of PCH) for this link entry.
Reserved
Datasheet, Volume 2