Dsts-Device Status Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.6.37 DSTS—Device Status Register
Reflects status corresponding to controls in the Device Control register. The error
reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:6
5
4:4
3
2
1
0
110
0/1/0–2/PCI
AA–ABh
0000h
RW1C, RO
16 bits
000h
Reset RST/
Attr
Value PWR
RO 0h
RO 0b Uncore
RO 0h
RW1C 0b Uncore
RW1C 0b Uncore
RW1C 0b Uncore
RW1C 0b Uncore
Processor Configuration Registers
Description
Reserved
Transactions Pending (TP)
0 = All pending transactions (including completions for any
outstanding non-posted requests on any used virtual channel)
have been completed.
1 = Indicates that the device has transaction(s) pending
(including completions for any outstanding non-posted
requests for all used Traffic Classes).
Not Applicable or Implemented. Hardwired to 0.
Reserved
Unsupported Request Detected (URD)
When set this bit indicates that the Device received an
Unsupported Request. Errors are logged in this register regardless
of whether error reporting is enabled or not in the Device Control
Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal Error
Detected bit is set according to the setting of the Unsupported
Request Error Severity bit. In production systems setting the Fatal
Error Detected bit is not an option as support for AER will not be
reported.
Fatal Error Detected (FED)
When set this bit indicates that fatal error(s) were detected. Errors
are logged in this register regardless of whether error reporting is
enabled or not in the Device Control register. When Advanced Error
Handling is enabled, errors are logged in this register regardless of
the settings of the uncorrectable error mask register.
Non-Fatal Error Detected (NFED)
When set this bit indicates that non-fatal error(s) were detected.
Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the uncorrectable error mask
register.
Correctable Error Detected (CED)
When set this bit indicates that correctable error(s) were detected.
Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the correctable error mask
register.
Datasheet, Volume 2