Dmile2D-Dmi Link Entry 2 Description Register; Dmile2A-Dmi Link Entry 2 Address Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.12.17 DMILE2D—DMI Link Entry 2 Description Register
This register provides the first part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:24
23:16
15:2
1
0
2.12.18 DMILE2A—DMI Link Entry 2 Address Register
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:12
11:0
Datasheet, Volume 2
0/0/0/DMIBAR
60–63h
00000000h
RO, RW-O
32 bits
0000h
Reset RST/
Attr
Value PWR
RO 00h Uncore
RW-O 00h Uncore
RO 0h
RO 0b Uncore
RW-O 0b Uncore
0/0/0/DMIBAR
68–6Bh
00000000h
RW-O
32 bits
000h
Reset RST/
Attr
Value PWR
RW-O 00000h Uncore
RO 0h
Description
Target Port Number (TPN)
This field specifies the port number associated with the element
targeted by this link entry (Egress Port). The target port number is
with respect to the component that contains this element as
specified by the target component ID.
Target Component ID (TCID)
This field identifies the physical or logical component that is
targeted by this link entry.
BIOS Requirement: Must be initialized according to guidelines in
the PCI Express* Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
Reserved
Link Type (TXTYP)
This bit indicates that the link points to memory-mapped space (for
RCRB).
The link address specifies the 64-bit base address of the target
RCRB.
Link Valid (LV)
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
Description
Link Address (LA)
Memory mapped base address of the RCRB that is the target
element (Egress Port) for this link entry.
Reserved
197