Dmivc0Rctl-Dmi Vc0 Resource Control Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register
This register controls the resources associated with PCI Express Virtual Channel 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31
30:27
26:24
23:20
19:17
16:8
7
6:1
0
Datasheet, Volume 2
0/0/0/DMIBAR
14–17h
8000007Fh
RO, RW
32 bits
00000h
Reset RST/
Attr
Value PWR
RO 1b Uncore
RO 0h
RO 000b Uncore
RO 0h
RW 000b Uncore
RO 0h
RO 0b Uncore
RW 3Fh Uncore
RO 1b Uncore
Description
Virtual Channel 0 Enable (VC0E)
For VC0, this is hardwired to 1 and read only as VC0 can never be
disabled.
Reserved
Virtual Channel 0 ID (VC0ID)
Assigns a VC ID to the VC resource. For VC0, this is hardwired to 0
and read only.
Reserved
Port Arbitration Select (PAS)
Configures the VC resource to provide a particular Port Arbitration
service. Valid value for this field is a number corresponding to one
of the asserted bits in the Port Arbitration Capability field of the VC
resource. Because only bit 0 of that field is asserted.
This field will always be programmed to 1.
Reserved
Traffic Class m / Virtual Channel 0 Map (TCMVC0M)
Traffic Class / Virtual Channel 0 Map (TCVC0M)
Indicates the TCs (Traffic Classes) that are mapped to the VC
resource. Bit locations within this field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this
VC resource. When more than one bit in this field is set, it indicates
that multiple TCs are mapped to the VC resource. To remove one
or more TCs from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the TC labels
are targeted at the given Link.
Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M)
Traffic Class 0 is always routed to VC0.
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