Dmivcech-Dmi Virtual Channel Enhanced Capability Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Table 2-14. DMIBAR Register Address Map (Sheet 2 of 2)
Address
Offset
88–89h
8A–8Bh
8C–97h
98–99h
9A–9Bh
9C–D33h
D34–D37h
2.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability
Register
This register indicates DMI Virtual Channel capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:20
19:16
15:0
186
Register
Symbol
LCTL Link Control
LSTS DMI Link Status
RSVD Reserved
Link Control 2
LCTL2
LSTS2 Link Status 2
RSVD Reserved
RSVD Reserved
0/0/0/DMIBAR
0–3h
04010002h
RO
32 bits
Reset RST/
Attr
Value PWR
RO 040h Uncore
RO 1h Uncore
RO 0002h Uncore
Processor Configuration Registers
Register Name
Description
Pointer to Next Capability (PNC)
This field contains the offset to the next PCI Express capability
structure in the linked list of capabilities (Link Declaration
Capability).
PCI Express Virtual Channel Capability Version (PCIEVCCV)
Hardwired to 1 to indicate compliances with the 1.1 version of the
PCI Express specification.
Note: This version does not change for 2.0 compliance.
Extended Capability ID (ECID)
The value of 0002h identifies this linked list item (capability
structure) as being for PCI Express Virtual Channel registers.
Reset
Access
Value
0000h RW, RW-V
0001h RO-V
0h RO
RWS,
0002h
RWS-V
0000h RO-V
0h RO
0000005Fh RW, RW1CS
Datasheet, Volume 2