System Memory Interface; Memory Channel A - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011 Datasheet

6.1

System Memory Interface

Table 6-2.

Memory Channel A

Signal Name
SA_BS[2:0]
SA_WE#
SA_RAS#
SA_CAS#
SA_DQS[8:0]
SA_DQS#[8:0]
SA_DQ[63:0]
SA_MA[15:0]
SA_CK[3:0]
SA_CK#[3:0]
SA_CKE[3:0]
SA_CS#[3:0]
SA_ODT[3:0]
60
Description
Bank Select: These signals define which banks are selected within
each SDRAM rank.
Write Enable Control Signal: This signal is used with SA_RAS# and
SA_CAS# (along with SA_CS#) to define the SDRAM Commands.
RAS Control Signal: This signal is used with SA_CAS# and SA_WE#
(along with SA_CS#) to define the SRAM Commands.
CAS Control Signal: This signal is used with SA_RAS# and SA_WE#
(along with SA_CS#) to define the SRAM Commands.
Data Strobes: SA_DQS[8:0] and its complement signal group make
up a differential strobe pair. The data is captured at the crossing point
of SA_DQS[8:0] and its SA_DQS#[8:0] during read and write
transactions.
Data Bus: Channel A data signal interface to the SDRAM data bus.
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM.
SDRAM Differential Clock: Channel A SDRAM Differential clock signal
pair. The crossing of the positive edge of SA_CK and the negative edge
of its complement SA_CK# are used to sample the command and
control signals on the SDRAM.
SDRAM Inverted Differential Clock: Channel A SDRAM Differential
clock signal-pair complement.
Clock Enable: (1 per rank). Used to:
• Initialize the SDRAMs during power-up
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh during STR
Chip Select: (1 per rank). Used to select particular SDRAM
components during the active state. There is one Chip Select for each
SDRAM rank.
On Die Termination: Active Termination Control.
Signal Description
Direction/
Buffer Type
O
DDR3
O
DDR3
O
DDR3
O
DDR3
I/O
DDR3
I/O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
Datasheet, Volume 1