Mbase1-Memory Base Address Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.6.15 MBASE1—Memory Base Address Register
This register controls the processor to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE  address  MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode, address bits A[19:0] are assumed to be
0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB
boundary.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:4
3:0
94
0/1/0–2/PCI
20–21h
FFF0h
RW
16 bits
0h
Reset RST/
Attr
Value PWR
RW FFFh Uncore
RO 0h
Processor Configuration Registers
Description
Memory Address Base (MBASE)
This field corresponds to A[31:20] of the lower limit of the memory
range that will be passed to PCI Express-G.
Reserved
Datasheet, Volume 2