Iobase1-I/O Base Address Register; Iolimit1-I/O Limit Address Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

2.6.12 IOBASE1—I/O Base Address Register
This register controls the processor to PCI Express-G I/O access routing based on the
following formula:
IO_BASE  address  IO_LIMIT
Only the upper 4 bits are programmable. For the purpose of address decode, address
bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
7:4
3:0
2.6.13 IOLIMIT1—I/O Limit Address Register
This register controls the processor to PCI Express-G I/O access routing based on the
following formula:
IO_BASE  address  IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode, address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4 KB aligned address block.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
7:4
3:0
92
0/1/0–2/PCI
1Ch
F0h
RW
8 bits
0h
Reset RST/
Attr
Value PWR
RW Fh Uncore
RO 0h
0/1/0–2/PCI
1Dh
00h
RW
8 bits
0h
Reset RST/
Attr
Value PWR
RW 0h Uncore
RO 0h
Processor Configuration Registers
Description
I/O Address Base (IOBASE)
This field corresponds to A[15:12] of the I/O addresses passed by
the root port to PCI Express-G.
Reserved
Description
I/O Address Limit (IOLIMIT)
This field corresponds to A[15:12] of the I/O address limit of the
root port. Devices between this upper limit and IOBASE1 will be
passed to the PCI Express hierarchy associated with this device.
Reserved
Datasheet, Volume 2